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wdenk5da627a2003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5da627a2003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
16#define CONFIG_DBAU1X00 1
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090017#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk5da627a2003-10-09 20:09:04 +000018
wdenka2663ea2003-12-07 18:32:37 +000019#ifdef CONFIG_DBAU1000
wdenk5da627a2003-10-09 20:09:04 +000020/* Also known as Merlot */
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090021#define CONFIG_SOC_AU1000 1
wdenka2663ea2003-12-07 18:32:37 +000022#else
23#ifdef CONFIG_DBAU1100
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090024#define CONFIG_SOC_AU1100 1
wdenka2663ea2003-12-07 18:32:37 +000025#else
26#ifdef CONFIG_DBAU1500
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090027#define CONFIG_SOC_AU1500 1
wdenkd4ca31c2004-01-02 14:00:00 +000028#else
wdenkff36fd82005-01-09 22:28:56 +000029#ifdef CONFIG_DBAU1550
30/* Cabernet */
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090031#define CONFIG_SOC_AU1550 1
wdenkff36fd82005-01-09 22:28:56 +000032#else
wdenka2663ea2003-12-07 18:32:37 +000033#error "No valid board set"
34#endif
35#endif
36#endif
wdenkff36fd82005-01-09 22:28:56 +000037#endif
wdenk5da627a2003-10-09 20:09:04 +000038
wdenkd4ca31c2004-01-02 14:00:00 +000039#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
wdenk5da627a2003-10-09 20:09:04 +000040
41#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
42
43#define CONFIG_BAUDRATE 115200
44
45/* valid baudrates */
wdenk5da627a2003-10-09 20:09:04 +000046
47#define CONFIG_TIMESTAMP /* Print image info with timestamp */
48#undef CONFIG_BOOTARGS
49
50#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "addmisc=setenv bootargs ${bootargs} " \
52 "console=ttyS0,${baudrate} " \
wdenk5da627a2003-10-09 20:09:04 +000053 "panic=1\0" \
54 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "load=tftp 80500000 ${u-boot}\0" \
wdenk5da627a2003-10-09 20:09:04 +000056 ""
wdenkff36fd82005-01-09 22:28:56 +000057
58#ifdef CONFIG_DBAU1550
59/* Boot from flash by default, revert to bootp */
60#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenkff36fd82005-01-09 22:28:56 +000061#else /* CONFIG_DBAU1550 */
Heiko Schocherad882972006-04-11 14:53:29 +020062#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenkff36fd82005-01-09 22:28:56 +000063#endif /* CONFIG_DBAU1550 */
64
Jon Loeligerab999ba2007-07-04 22:32:03 -050065
66/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050067 * BOOTP options
68 */
69#define CONFIG_BOOTP_BOOTFILESIZE
70#define CONFIG_BOOTP_BOOTPATH
71#define CONFIG_BOOTP_GATEWAY
72#define CONFIG_BOOTP_HOSTNAME
73
74
75/*
Jon Loeligerab999ba2007-07-04 22:32:03 -050076 * Command line configuration.
77 */
78#include <config_cmd_default.h>
79
80#undef CONFIG_CMD_BDI
81#undef CONFIG_CMD_BEDBUG
82#undef CONFIG_CMD_ELF
Mike Frysingerbdab39d2009-01-28 19:08:14 -050083#undef CONFIG_CMD_SAVEENV
Jon Loeligerab999ba2007-07-04 22:32:03 -050084#undef CONFIG_CMD_FAT
85#undef CONFIG_CMD_FPGA
86#undef CONFIG_CMD_MII
87#undef CONFIG_CMD_RUN
88
89
90#ifdef CONFIG_DBAU1550
91
92#define CONFIG_CMD_FLASH
93#define CONFIG_CMD_LOADB
94#define CONFIG_CMD_NET
95
96#undef CONFIG_CMD_I2C
97#undef CONFIG_CMD_IDE
98#undef CONFIG_CMD_NFS
99#undef CONFIG_CMD_PCMCIA
100
101#else
102
103#define CONFIG_CMD_IDE
104#define CONFIG_CMD_DHCP
105
106#undef CONFIG_CMD_FLASH
107#undef CONFIG_CMD_LOADB
108#undef CONFIG_CMD_LOADS
109
110#endif
111
wdenk5da627a2003-10-09 20:09:04 +0000112
113/*
114 * Miscellaneous configurable options
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkff36fd82005-01-09 22:28:56 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
wdenkff36fd82005-01-09 22:28:56 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
122#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk5da627a2003-10-09 20:09:04 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk5da627a2003-10-09 20:09:04 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk5da627a2003-10-09 20:09:04 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MHZ 396
wdenkff36fd82005-01-09 22:28:56 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#if (CONFIG_SYS_MHZ % 12) != 0
wdenkff36fd82005-01-09 22:28:56 +0000131#error "Invalid CPU frequency - must be multiple of 12!"
132#endif
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashia55d4812008-06-05 22:29:00 +0900135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk5da627a2003-10-09 20:09:04 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk5da627a2003-10-09 20:09:04 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MEMTEST_START 0x80100000
141#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk5da627a2003-10-09 20:09:04 +0000142
143/*-----------------------------------------------------------------------
144 * FLASH and environment organization
145 */
wdenkff36fd82005-01-09 22:28:56 +0000146#ifdef CONFIG_DBAU1550
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
149#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenkff36fd82005-01-09 22:28:56 +0000150
151#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
152#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
153
wdenkff36fd82005-01-09 22:28:56 +0000154#else /* CONFIG_DBAU1550 */
155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
157#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk5da627a2003-10-09 20:09:04 +0000158
159#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
160#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
161
wdenkff36fd82005-01-09 22:28:56 +0000162#endif /* CONFIG_DBAU1550 */
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocherad882972006-04-11 14:53:29 +0200165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200167#define CONFIG_FLASH_CFI_DRIVER 1
wdenkff36fd82005-01-09 22:28:56 +0000168
wdenk5da627a2003-10-09 20:09:04 +0000169/* The following #defines are needed to get flash environment right */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200170#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk5da627a2003-10-09 20:09:04 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk5da627a2003-10-09 20:09:04 +0000174
175/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk5da627a2003-10-09 20:09:04 +0000177
178/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
180#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk5da627a2003-10-09 20:09:04 +0000181
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200182#define CONFIG_ENV_IS_NOWHERE 1
wdenk5da627a2003-10-09 20:09:04 +0000183
184/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_ADDR 0xB0030000
186#define CONFIG_ENV_SIZE 0x10000
wdenk5da627a2003-10-09 20:09:04 +0000187
188#define CONFIG_FLASH_16BIT
189
190#define CONFIG_NR_DRAM_BANKS 2
191
wdenk5da627a2003-10-09 20:09:04 +0000192
wdenkff36fd82005-01-09 22:28:56 +0000193#ifdef CONFIG_DBAU1550
194#define MEM_SIZE 192
195#else
196#define MEM_SIZE 64
197#endif
198
wdenk5da627a2003-10-09 20:09:04 +0000199#define CONFIG_MEMSIZE_IN_BYTES
200
wdenkff36fd82005-01-09 22:28:56 +0000201#ifndef CONFIG_DBAU1550
wdenk5da627a2003-10-09 20:09:04 +0000202/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
204#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk5da627a2003-10-09 20:09:04 +0000205#define CONFIG_PCMCIA_SLOT_A
206
207#define CONFIG_ATAPI 1
208#define CONFIG_MAC_PARTITION 1
209
210/* We run CF in "true ide" mode or a harddrive via pcmcia */
211#define CONFIG_IDE_PCMCIA 1
212
213/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
215#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk5da627a2003-10-09 20:09:04 +0000216
217#undef CONFIG_IDE_LED /* LED for ide not supported */
218#undef CONFIG_IDE_RESET /* reset for ide not supported */
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk5da627a2003-10-09 20:09:04 +0000221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk5da627a2003-10-09 20:09:04 +0000223
wdenkd4ca31c2004-01-02 14:00:00 +0000224/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk5da627a2003-10-09 20:09:04 +0000226
227/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk5da627a2003-10-09 20:09:04 +0000229
230/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkff36fd82005-01-09 22:28:56 +0000232#endif /* CONFIG_DBAU1550 */
wdenk5da627a2003-10-09 20:09:04 +0000233
234/*-----------------------------------------------------------------------
235 * Cache Configuration
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_DCACHE_SIZE 16384
238#define CONFIG_SYS_ICACHE_SIZE 16384
239#define CONFIG_SYS_CACHELINE_SIZE 32
wdenk5da627a2003-10-09 20:09:04 +0000240
wdenk5da627a2003-10-09 20:09:04 +0000241#endif /* __CONFIG_H */