blob: 5c6188955d6a98bf184aed5b6091815791da012b [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -040012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
18
19/*-----------------------------------------------------------------------------
20High Level Configuration Options
21(easy to change)
22-----------------------------------------------------------------------------*/
23#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
24#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
25#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
26#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
27 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028
29/*
30 * Valid values for CONFIG_SYS_TEXT_BASE are:
31 * 0xFFF00000 boot high (standard configuration)
32 * 0xFF000000 boot low
33 * 0x00100000 boot from RAM (for testing only)
34 */
35#ifndef CONFIG_SYS_TEXT_BASE
36#define CONFIG_SYS_TEXT_BASE 0xFFF00000
37#endif
38
Jon Smirlc9969942009-06-14 18:21:28 -040039#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -040040
41/*-----------------------------------------------------------------------------
42Serial console configuration
43-----------------------------------------------------------------------------*/
44#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
45 /*define gps port conf. */
46 /* register later on to */
47 /*enable UART function! */
48#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
49#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
50
51/*
52 * Command line configuration.
53 */
54#include <config_cmd_default.h>
55
56#define CONFIG_CMD_DATE
57#define CONFIG_CMD_DHCP
58#define CONFIG_CMD_EEPROM
59#define CONFIG_CMD_I2C
60#define CONFIG_CMD_JFFS2
61#define CONFIG_CMD_MII
62#define CONFIG_CMD_NFS
63#define CONFIG_CMD_PCI
64
65#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
66
Wolfgang Denk14d0a022010-10-07 21:51:12 +020067#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -040068#define CONFIG_SYS_LOWBOOT 1
69#endif
70/* RAMBOOT will be defined automatically in memory section */
71
72#define CONFIG_JFFS2_CMDLINE
73#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
74#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
75 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
76
77/*-----------------------------------------------------------------------------
78Autobooting
79-----------------------------------------------------------------------------*/
80#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
81#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
82 /* even with bootdelay=0 */
83#undef CONFIG_BOOTARGS
84
85
86#define CONFIG_PREBOOT "echo;" \
87 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
88 "mount root filesystem over NFS;" \
89 "echo"
90
91#define CONFIG_EXTRA_ENV_SETTINGS \
92 "netdev=eth0\0" \
93 "uimage=uImage-pcm030\0" \
94 "oftree=oftree-pcm030.dtb\0" \
95 "jffs2=root-pcm030.jffs2\0" \
96 "uboot=u-boot-pcm030.bin\0" \
97 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
98 " $(mtdparts) rw\0" \
99 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
100 " rootfstype=jffs2\0" \
101 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
102 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
103 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
104 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
105 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
106 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
107 "0xfff40000\0" \
108 " cp.b 0x400000 0xff040000 $(filesize)\0" \
109 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
110 "cp.b 0x400000 0xff200000 $(filesize)\0" \
111 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
112 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
113 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
114 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
115 "unlock=yes\0" \
116 ""
117
118#define CONFIG_BOOTCOMMAND "run bcmd_flash"
119
120/*--------------------------------------------------------------------------
121IPB Bus clocking configuration.
122 ---------------------------------------------------------------------------*/
123#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
124
125/*-------------------------------------------------------------------------
126 * PCI Mapping:
127 * 0x40000000 - 0x4fffffff - PCI Memory
128 * 0x50000000 - 0x50ffffff - PCI IO Space
129 * -----------------------------------------------------------------------*/
130#define CONFIG_PCI 1
131#define CONFIG_PCI_PNP 1
132#define CONFIG_PCI_SCAN_SHOW 1
133#define CONFIG_PCI_MEM_BUS 0x40000000
134#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
135#define CONFIG_PCI_MEM_SIZE 0x10000000
136#define CONFIG_PCI_IO_BUS 0x50000000
137#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
138#define CONFIG_PCI_IO_SIZE 0x01000000
139#define CONFIG_SYS_XLB_PIPELINING 1
140
141/*---------------------------------------------------------------------------
142 I2C configuration
143---------------------------------------------------------------------------*/
144#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
145#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
146#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
147#define CONFIG_SYS_I2C_SLAVE 0x7F
148
149/*---------------------------------------------------------------------------
150 EEPROM CAT24WC32 configuration
151---------------------------------------------------------------------------*/
152#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
153#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
154#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
155#define CONFIG_SYS_EEPROM_SIZE 2048
156#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
157#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
158
159/*---------------------------------------------------------------------------
160RTC configuration
161---------------------------------------------------------------------------*/
162#define RTC
163#define CONFIG_RTC_PCF8563 1
164#define CONFIG_SYS_I2C_RTC_ADDR 0x51
165
166/*---------------------------------------------------------------------------
167 Flash configuration
168---------------------------------------------------------------------------*/
169
170#define CONFIG_SYS_FLASH_BASE 0xff000000
171#define CONFIG_SYS_FLASH_SIZE 0x01000000
172#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
173
174#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
175#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
176#define CONFIG_SYS_FLASH_EMPTY_INFO
177#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
178#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
179 /* (= chip selects) */
180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
181
182/*
183 * Use also hardware protection. This seems required, as the BDI uses
184 * hardware protection. Without this, U-Boot can't work with this sectors,
185 * as its protection is software only by default
186 */
187#define CONFIG_SYS_FLASH_PROTECTION 1
188
189/*---------------------------------------------------------------------------
190 Environment settings
191---------------------------------------------------------------------------*/
192
193/* pcm030 ships with environment is EEPROM by default */
194#define CONFIG_ENV_IS_IN_EEPROM 1
195#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
196 /*beginning of the EEPROM */
197#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
198
199#define CONFIG_ENV_OVERWRITE 1
200
201/*-----------------------------------------------------------------------------
202 Memory map
203-----------------------------------------------------------------------------*/
204#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
205 /* bootloader or debugger config */
206#define CONFIG_SYS_SDRAM_BASE 0x00000000
207#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
208/* Use SRAM until RAM will be available */
209#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400211 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200213 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400214#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
215
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200216#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400217#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
218# define CONFIG_SYS_RAMBOOT 1
219#endif
220
221#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
222#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
223#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224
225/*-----------------------------------------------------------------------------
226 Ethernet configuration
227-----------------------------------------------------------------------------*/
228#define CONFIG_MPC5xxx_FEC 1
229#define CONFIG_MPC5xxx_FEC_MII100
230#define CONFIG_PHY_ADDR 0x01
231
232/*---------------------------------------------------------------------------
233 GPIO configuration
234 ---------------------------------------------------------------------------*/
235
236/* GPIO port configuration
237 *
238 * Pin mapping:
239 *
240 * [29:31] = 01x
241 * PSC1_0 -> AC97 SDATA out
242 * PSC1_1 -> AC97 SDTA in
243 * PSC1_2 -> AC97 SYNC out
244 * PSC1_3 -> AC97 bitclock out
245 * PSC1_4 -> AC97 reset out
246 *
247 * [25:27] = 001
248 * PSC2_0 -> CAN 1 Tx out
249 * PSC2_1 -> CAN 1 Rx in
250 * PSC2_2 -> CAN 2 Tx out
251 * PSC2_3 -> CAN 2 Rx in
252 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
253 *
254 *
255 * [20:23] = 1100
256 * PSC3_0 -> UART Tx out
257 * PSC3_1 -> UART Rx in
258 * PSC3_2 -> UART RTS (in/out FIXME)
259 * PSC3_3 -> UART CTS (in/out FIXME)
260 * PSC3_4 -> LocalPlus Bus CS6 \
261 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
262 * PSC3_6 -> dedicated SPI MOSI out (master case)
263 * PSC3_7 -> dedicated SPI MISO in (master case)
264 * PSC3_8 -> dedicated SPI SS out (master case)
265 * PSC3_9 -> dedicated SPI CLK out (master case)
266 *
267 * [18:19] = 01
268 * USB_0 -> USB OE out
269 * USB_1 -> USB Tx- out
270 * USB_2 -> USB Tx+ out
271 * USB_3 -> USB RxD (in/out FIXME)
272 * USB_4 -> USB Rx+ in
273 * USB_5 -> USB Rx- in
274 * USB_6 -> USB PortPower out
275 * USB_7 -> USB speed out
276 * USB_8 -> USB suspend (in/out FIXME)
277 * USB_9 -> USB overcurrent in
278 *
279 * [17] = 0
280 * USB differential mode
281 *
282 * [16] = 0
283 * PCI enabled
284 *
285 * [12:15] = 0101
286 * ETH_0 -> ETH Txen
287 * ETH_1 -> ETH TxD0
288 * ETH_2 -> ETH TxD1
289 * ETH_3 -> ETH TxD2
290 * ETH_4 -> ETH TxD3
291 * ETH_5 -> ETH Txerr
292 * ETH_6 -> ETH MDC
293 * ETH_7 -> ETH MDIO
294 * ETH_8 -> ETH RxDv
295 * ETH_9 -> ETH RxCLK
296 * ETH_10 -> ETH Collision
297 * ETH_11 -> ETH TxD
298 * ETH_12 -> ETH RxD0
299 * ETH_13 -> ETH RxD1
300 * ETH_14 -> ETH RxD2
301 * ETH_15 -> ETH RxD3
302 * ETH_16 -> ETH Rxerr
303 * ETH_17 -> ETH CRS
304 *
305 * [9:11] = 101
306 * PSC6_0 -> UART RxD in
307 * PSC6_1 -> UART CTS (in/out FIXME)
308 * PSC6_2 -> UART TxD out
309 * PSC6_3 -> UART RTS (in/out FIXME)
310 *
311 * [2:3/6:7] = 00/11
312 * TMR_0 -> ATA_CS0 out
313 * TMR_1 -> ATA_CS1 out
314 * TMR_2 -> GPIO
315 * TMR_3 -> GPIO
316 * TMR_4 -> GPIO
317 * TMR_5 -> GPIO
318 * TMR_6 -> GPIO
319 * TMR_7 -> GPIO
320 * I2C_0 -> I2C 1 Clock out
321 * I2C_1 -> I2C 1 IO in/out
322 * I2C_2 -> I2C 2 Clock out
323 * I2C_3 -> I2C 2 IO in/out
324 *
325 * [4] = 1
326 * PSC3_5 is used as CS7
327 *
328 * [5] = 1
329 * PSC3_4 is used as CS6
330 *
331 * [1] = 0
332 * gpio_wkup_7 is GPIO
333 *
334 * [0] = 0
335 * gpio_wkup_6 is GPIO
336 *
337 */
338#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
339
340/*-----------------------------------------------------------------------------
341 Miscellaneous configurable options
342-------------------------------------------------------------------------------*/
343#define CONFIG_SYS_LONGHELP /* undef to save memory */
344#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
345
346#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
347
348#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
349#if defined(CONFIG_CMD_KGDB)
350#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
351#endif
352
353#if defined(CONFIG_CMD_KGDB)
354#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
355#else
356#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
357#endif
358#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
359 /* Print Buffer Size */
360#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
361#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
362
363#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
364#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
365
366#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Jon Smirlc9969942009-06-14 18:21:28 -0400367
368#define CONFIG_DISPLAY_BOARDINFO 1
369
370/*-----------------------------------------------------------------------------
371 Various low-level settings
372-----------------------------------------------------------------------------*/
373#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
374#define CONFIG_SYS_HID0_FINAL HID0_ICE
375
376/* no burst access on the LPB */
377#define CONFIG_SYS_CS_BURST 0x00000000
378/* one deadcycle for the 33MHz statemachine */
379#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
380/* one additional waitstate for the 33MHz statemachine */
381#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
382#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
383#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
384
385#define CONFIG_SYS_RESET_ADDRESS 0xff000000
386
387/*-----------------------------------------------------------------------
388 * USB stuff
389 *-----------------------------------------------------------------------
390 */
391#define CONFIG_USB_CLOCK 0x0001BBBB
392#define CONFIG_USB_CONFIG 0x00001000
393
394/*---------------------------------------------------------------------------
395 IDE/ATA stuff Supports IDE harddisk
396----------------------------------------------------------------------------*/
397
398#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
399#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
400#undef CONFIG_IDE_LED /* LED for ide not supported */
401#define CONFIG_SYS_ATA_CS_ON_TIMER01
402#define CONFIG_IDE_RESET 1 /* reset for ide supported */
403#define CONFIG_IDE_PREINIT
404#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
405#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
406#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
407#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
408/* Offset for data I/O */
409#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
410/* Offset for normal register accesses */
411#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
412/* Offset for alternate registers */
413#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
414/* Interval between registers */
415#define CONFIG_SYS_ATA_STRIDE 4
416#define CONFIG_ATAPI 1
417
418/* we enable IDE and FAT support, so we also need partition support */
419#define CONFIG_DOS_PARTITION 1
420
421/* USB */
422#define CONFIG_USB_OHCI
423#define CONFIG_USB_STORAGE
424
425/* pass open firmware flat tree */
426#define CONFIG_OF_LIBFDT 1
427#define CONFIG_OF_BOARD_SETUP 1
428
429#define OF_CPU "PowerPC,5200@0"
430#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
431#define OF_SOC "soc5200@f0000000"
432#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
433
434#endif /* __CONFIG_H */