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Ilko Iliev32949232009-06-12 21:20:39 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Ilko Iliev32949232009-06-12 21:20:39 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9261 board.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Ilko Iliev32949232009-06-12 21:20:39 +020010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Asen Dimovf47316a2011-07-26 04:48:41 +000015/*
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
18 */
19
20#include <asm/hardware.h>
Ilko Iliev32949232009-06-12 21:20:39 +020021/* ARM asynchronous clock */
Ilko Iliev32949232009-06-12 21:20:39 +020022
23#define CONFIG_DISPLAY_BOARDINFO
24
25#define MASTER_PLL_DIV 15
26#define MASTER_PLL_MUL 162
27#define MAIN_PLL_DIV 2
Asen Dimovf47316a2011-07-26 04:48:41 +000028#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010029#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Ilko Iliev32949232009-06-12 21:20:39 +020030
Asen Dimovf47316a2011-07-26 04:48:41 +000031#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
Ilko Iliev32949232009-06-12 21:20:39 +020032#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
33#define CONFIG_ARCH_CPU_INIT
Asen Dimov4f81bf42010-12-12 12:41:30 +020034#define CONFIG_SYS_TEXT_BASE 0
Ilko Iliev32949232009-06-12 21:20:39 +020035
Asen Dimova3e09cc2011-10-31 08:54:20 +000036#define MACH_TYPE_PM9261 1187
37#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
38
Ilko Iliev32949232009-06-12 21:20:39 +020039/* clocks */
40/* CKGR_MOR - enable main osc. */
41#define CONFIG_SYS_MOR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030042 (AT91_PMC_MOR_MOSCEN | \
Ilko Iliev32949232009-06-12 21:20:39 +020043 (255 << 8)) /* Main Oscillator Start-up Time */
44#define CONFIG_SYS_PLLAR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030045 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
46 AT91_PMC_PLLXR_OUT(3) | \
Ilko Iliev32949232009-06-12 21:20:39 +020047 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
48
49/* PCK/2 = MCK Master Clock from PLLA */
50#define CONFIG_SYS_MCKR1_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030051 (AT91_PMC_MCKR_CSS_SLOW | \
52 AT91_PMC_MCKR_PRES_1 | \
53 AT91_PMC_MCKR_MDIV_2 | \
54 AT91_PMC_MCKR_PLLADIV_1)
Ilko Iliev32949232009-06-12 21:20:39 +020055
56/* PCK/2 = MCK Master Clock from PLLA */
57#define CONFIG_SYS_MCKR2_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030058 (AT91_PMC_MCKR_CSS_PLLA | \
59 AT91_PMC_MCKR_PRES_1 | \
60 AT91_PMC_MCKR_MDIV_2 | \
61 AT91_PMC_MCKR_PLLADIV_1)
Ilko Iliev32949232009-06-12 21:20:39 +020062
63/* define PDC[31:16] as DATA[31:16] */
64#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
65/* no pull-up for D[31:16] */
66#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
67
68/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
69#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030070 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
Ilko Iliev32949232009-06-12 21:20:39 +020071
72/* SDRAM */
73/* SDRAMC_MR Mode register */
74#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
75/* SDRAMC_TR - Refresh Timer register */
76#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
77/* SDRAMC_CR - Configuration register*/
78#define CONFIG_SYS_SDRC_CR_VAL \
79 (AT91_SDRAMC_NC_9 | \
80 AT91_SDRAMC_NR_13 | \
81 AT91_SDRAMC_NB_4 | \
82 AT91_SDRAMC_CAS_3 | \
83 AT91_SDRAMC_DBW_32 | \
84 (1 << 8) | /* Write Recovery Delay */ \
85 (7 << 12) | /* Row Cycle Delay */ \
86 (3 << 16) | /* Row Precharge Delay */ \
87 (2 << 20) | /* Row to Column Delay */ \
88 (5 << 24) | /* Active to Precharge Delay */ \
89 (1 << 28)) /* Exit Self Refresh to Active Delay */
90
91/* Memory Device Register -> SDRAM */
92#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
93#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
94#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
95#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
96#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
97#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
98#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
99#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
100#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
101#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
102#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
103#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
104#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
105#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
106#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
107#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
108#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
109#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
110
111/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
112#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300113 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
114 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Ilko Iliev32949232009-06-12 21:20:39 +0200115#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300116 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
117 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Ilko Iliev32949232009-06-12 21:20:39 +0200118#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300119 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Ilko Iliev32949232009-06-12 21:20:39 +0200120#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300121 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
122 AT91_SMC_MODE_DBW_16 | \
123 AT91_SMC_MODE_TDF | \
124 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Iliev32949232009-06-12 21:20:39 +0200125
126/* user reset enable */
127#define CONFIG_SYS_RSTC_RMR_VAL \
128 (AT91_RSTC_KEY | \
Asen Dimove3150c72010-04-06 16:18:04 +0300129 AT91_RSTC_CR_PROCRST | \
130 AT91_RSTC_MR_ERSTL(1) | \
131 AT91_RSTC_MR_ERSTL(2))
Ilko Iliev32949232009-06-12 21:20:39 +0200132
133/* Disable Watchdog */
134#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300135 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
136 AT91_WDT_MR_WDV(0xfff) | \
137 AT91_WDT_MR_WDDIS | \
138 AT91_WDT_MR_WDD(0xfff))
Ilko Iliev32949232009-06-12 21:20:39 +0200139
140#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
141#define CONFIG_SETUP_MEMORY_TAGS 1
142#define CONFIG_INITRD_TAG 1
143
144#undef CONFIG_SKIP_LOWLEVEL_INIT
Asen Dimov0160c1e2011-12-09 10:59:07 +0000145#define CONFIG_BOARD_EARLY_INIT_F
Ilko Iliev32949232009-06-12 21:20:39 +0200146
147/*
148 * Hardware drivers
149 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100150#define CONFIG_AT91_GPIO 1
Ilko Iliev32949232009-06-12 21:20:39 +0200151#define CONFIG_ATMEL_USART 1
Asen Dimovf47316a2011-07-26 04:48:41 +0000152#define CONFIG_USART_BASE ATMEL_BASE_DBGU
153#define CONFIG_USART_ID ATMEL_ID_SYS
Ilko Iliev32949232009-06-12 21:20:39 +0200154
155/* LCD */
156#define CONFIG_LCD 1
157#define LCD_BPP LCD_COLOR8
158#define CONFIG_LCD_LOGO 1
159#undef LCD_TEST_PATTERN
160#define CONFIG_LCD_INFO 1
161#define CONFIG_LCD_INFO_BELOW_LOGO 1
162#define CONFIG_SYS_WHITE_ON_BLACK 1
163#define CONFIG_ATMEL_LCD 1
164#define CONFIG_ATMEL_LCD_BGR555 1
165#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
166
167/* LED */
168#define CONFIG_AT91_LED
Asen Dimove3150c72010-04-06 16:18:04 +0300169#define CONFIG_RED_LED AT91_PIO_PORTC, 12
170#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13
171#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15
Ilko Iliev32949232009-06-12 21:20:39 +0200172
173#define CONFIG_BOOTDELAY 3
174
175/*
176 * BOOTP options
177 */
178#define CONFIG_BOOTP_BOOTFILESIZE 1
179#define CONFIG_BOOTP_BOOTPATH 1
180#define CONFIG_BOOTP_GATEWAY 1
181#define CONFIG_BOOTP_HOSTNAME 1
182
183/*
184 * Command line configuration.
185 */
186#include <config_cmd_default.h>
187#undef CONFIG_CMD_BDI
188#undef CONFIG_CMD_IMI
Ilko Iliev32949232009-06-12 21:20:39 +0200189#undef CONFIG_CMD_FPGA
190#undef CONFIG_CMD_LOADS
191#undef CONFIG_CMD_IMLS
192
Asen Dimov6741b532010-12-12 12:41:36 +0200193#define CONFIG_CMD_CACHE
Ilko Iliev32949232009-06-12 21:20:39 +0200194#define CONFIG_CMD_PING 1
195#define CONFIG_CMD_DHCP 1
196#define CONFIG_CMD_NAND 1
197#define CONFIG_CMD_USB 1
198
199/* SDRAM */
200#define CONFIG_NR_DRAM_BANKS 1
201#define PHYS_SDRAM 0x20000000
202#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
203
204/* DataFlash */
205#define CONFIG_ATMEL_DATAFLASH_SPI
206#define CONFIG_HAS_DATAFLASH
207#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
208#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
209#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
210#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
211#define AT91_SPI_CLK 15000000
212#define DATAFLASH_TCSS (0x1a << 16)
213#define DATAFLASH_TCHS (0x1 << 24)
214
215/* NAND flash */
216#define CONFIG_NAND_ATMEL
Ilko Iliev32949232009-06-12 21:20:39 +0200217#define CONFIG_SYS_MAX_NAND_DEVICE 1
218#define CONFIG_SYS_NAND_BASE 0x40000000
219#define CONFIG_SYS_NAND_DBW_8 1
220/* our ALE is AD22 */
221#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
222/* our CLE is AD21 */
223#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
Asen Dimove3150c72010-04-06 16:18:04 +0300224#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
225#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
Ilko Iliev32949232009-06-12 21:20:39 +0200226
Ilko Iliev32949232009-06-12 21:20:39 +0200227/* NOR flash */
228#define CONFIG_SYS_FLASH_CFI 1
229#define CONFIG_FLASH_CFI_DRIVER 1
230#define PHYS_FLASH_1 0x10000000
231#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
232#define CONFIG_SYS_MAX_FLASH_SECT 256
233#define CONFIG_SYS_MAX_FLASH_BANKS 1
234
235/* Ethernet */
236#define CONFIG_DRIVER_DM9000 1
237#define CONFIG_DM9000_BASE 0x30000000
238#define DM9000_IO CONFIG_DM9000_BASE
239#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
240#define CONFIG_DM9000_USE_16BIT 1
241#define CONFIG_NET_RETRY_COUNT 20
242#define CONFIG_RESET_PHY_R 1
Ilko Iliev32949232009-06-12 21:20:39 +0200243
244/* USB */
245#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800246#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ilko Iliev32949232009-06-12 21:20:39 +0200247#define CONFIG_USB_OHCI_NEW 1
248#define CONFIG_DOS_PARTITION 1
249#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
250#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
251#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
252#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
253#define CONFIG_USB_STORAGE 1
254
255#define CONFIG_SYS_LOAD_ADDR 0x22000000
256
257#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
258#define CONFIG_SYS_MEMTEST_END 0x23e00000
259
260#undef CONFIG_SYS_USE_DATAFLASH_CS0
261#undef CONFIG_SYS_USE_NANDFLASH
262#define CONFIG_SYS_USE_FLASH 1
263
264#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
265
266/* bootstrap + u-boot + env + linux in dataflash on CS0 */
267#define CONFIG_ENV_IS_IN_DATAFLASH 1
268#define CONFIG_SYS_MONITOR_BASE \
269 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
270#define CONFIG_ENV_OFFSET 0x4200
271#define CONFIG_ENV_ADDR \
272 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
273#define CONFIG_ENV_SIZE 0x4200
274#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
275#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
276 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200277 "mtdparts=atmel_nand:-(root) " \
Ilko Iliev32949232009-06-12 21:20:39 +0200278 "rw rootfstype=jffs2"
279
280#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
281
282/* bootstrap + u-boot + env + linux in nandflash */
283#define CONFIG_ENV_IS_IN_NAND 1
284#define CONFIG_ENV_OFFSET 0x60000
285#define CONFIG_ENV_OFFSET_REDUND 0x80000
286#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
287#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
288#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
289 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200290 "mtdparts=atmel_nand:128k(bootstrap)ro," \
Ilko Iliev32949232009-06-12 21:20:39 +0200291 "256k(uboot)ro,128k(env1)ro," \
292 "128k(env2)ro,2M(linux),-(root) " \
293 "rw rootfstype=jffs2"
294
295#elif defined (CONFIG_SYS_USE_FLASH)
296
297#define CONFIG_ENV_IS_IN_FLASH 1
298#define CONFIG_ENV_OFFSET 0x40000
299#define CONFIG_ENV_SECT_SIZE 0x10000
300#define CONFIG_ENV_SIZE 0x10000
301#define CONFIG_ENV_OVERWRITE 1
302
303/* JFFS Partition offset set */
304#define CONFIG_SYS_JFFS2_FIRST_BANK 0
305#define CONFIG_SYS_JFFS2_NUM_BANKS 1
306
307/* 512k reserved for u-boot */
308#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
309
310#define CONFIG_BOOTCOMMAND "run flashboot"
311
312#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
313#define MTDPARTS_DEFAULT \
314 "mtdparts=physmap-flash.0:" \
315 "256k(u-boot)ro," \
316 "64k(u-boot-env)ro," \
317 "1408k(kernel)," \
318 "-(rootfs);" \
319 "nand:-(nand)"
320
321#define CONFIG_CON_ROT "fbcon=rotate:3 "
322#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
323
324#define CONFIG_EXTRA_ENV_SETTINGS \
325 "mtdids=" MTDIDS_DEFAULT "\0" \
326 "mtdparts=" MTDPARTS_DEFAULT "\0" \
327 "partition=nand0,0\0" \
328 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
329 "nfsargs=setenv bootargs root=/dev/nfs rw " \
330 CONFIG_CON_ROT \
331 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
332 "addip=setenv bootargs $(bootargs) " \
333 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
334 ":$(hostname):eth0:off\0" \
335 "ramboot=tftpboot 0x22000000 vmImage;" \
336 "run ramargs;run addip;bootm 22000000\0" \
337 "nfsboot=tftpboot 0x22000000 vmImage;" \
338 "run nfsargs;run addip;bootm 22000000\0" \
339 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
340 ""
341#else
342#error "Undefined memory device"
343#endif
344
345#define CONFIG_BAUDRATE 115200
Ilko Iliev32949232009-06-12 21:20:39 +0200346
347#define CONFIG_SYS_PROMPT "pm9261> "
348#define CONFIG_SYS_CBSIZE 256
349#define CONFIG_SYS_MAXARGS 16
350#define CONFIG_SYS_PBSIZE \
351 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
352#define CONFIG_SYS_LONGHELP 1
353#define CONFIG_CMDLINE_EDITING 1
354
Ilko Iliev32949232009-06-12 21:20:39 +0200355/*
356 * Size of malloc() pool
357 */
358#define CONFIG_SYS_MALLOC_LEN \
359 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Ilko Iliev32949232009-06-12 21:20:39 +0200360
Asen Dimov4f81bf42010-12-12 12:41:30 +0200361#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
362#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
363 GENERATED_GBL_DATA_SIZE)
364
Ilko Iliev32949232009-06-12 21:20:39 +0200365#endif