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Ilko Ilievf0a2c7b2009-04-16 21:30:48 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9263 board.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Asen Dimov684a5672011-06-08 22:01:16 +000015/*
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
18 */
19#include <asm/hardware.h>
20
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020021/* ARM asynchronous clock */
Jean-Christophe PLAGNIOL-VILLARDb2403582009-05-31 14:53:18 +020022#define CONFIG_DISPLAY_CPUINFO
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020023#define CONFIG_DISPLAY_BOARDINFO
24
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020025#define MASTER_PLL_DIV 6
26#define MASTER_PLL_MUL 65
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020027#define MAIN_PLL_DIV 2 /* 2 or 4 */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010028#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Asen Dimov684a5672011-06-08 22:01:16 +000029#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020030
Asen Dimov684a5672011-06-08 22:01:16 +000031#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020032#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
33#define CONFIG_ARCH_CPU_INIT
Asen Dimov9a2a05a2010-12-12 12:41:59 +020034#define CONFIG_SYS_TEXT_BASE 0
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020035
Asen Dimova3e09cc2011-10-31 08:54:20 +000036#define MACH_TYPE_PM9263 1475
37#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
38
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020039/* clocks */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020040#define CONFIG_SYS_MOR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030041 (AT91_PMC_MOR_MOSCEN | \
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020042 (255 << 8)) /* Main Oscillator Start-up Time */
43#define CONFIG_SYS_PLLAR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030044 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
45 AT91_PMC_PLLXR_OUT(3) | \
46 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020047 (2 << 28) | /* PLL Clock Frequency Range */ \
48 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020049
50#if (MAIN_PLL_DIV == 2)
51/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020052#define CONFIG_SYS_MCKR1_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030053 (AT91_PMC_MCKR_CSS_SLOW | \
54 AT91_PMC_MCKR_PRES_1 | \
55 AT91_PMC_MCKR_MDIV_2)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020056/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020057#define CONFIG_SYS_MCKR2_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030058 (AT91_PMC_MCKR_CSS_PLLA | \
59 AT91_PMC_MCKR_PRES_1 | \
60 AT91_PMC_MCKR_MDIV_2)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020061#else
62/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020063#define CONFIG_SYS_MCKR1_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030064 (AT91_PMC_MCKR_CSS_SLOW | \
65 AT91_PMC_MCKR_PRES_1 | \
66 AT91_PMC_MCKR_MDIV_4)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020067/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020068#define CONFIG_SYS_MCKR2_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030069 (AT91_PMC_MCKR_CSS_PLLA | \
70 AT91_PMC_MCKR_PRES_1 | \
71 AT91_PMC_MCKR_MDIV_4)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020072#endif
73/* define PDC[31:16] as DATA[31:16] */
74#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
75/* no pull-up for D[31:16] */
76#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
77/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020078#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030079 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
80 AT91_MATRIX_CSA_EBI_CS1A)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020081
82/* SDRAM */
83/* SDRAMC_MR Mode register */
84#define CONFIG_SYS_SDRC_MR_VAL1 0
85/* SDRAMC_TR - Refresh Timer register */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020086#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
87/* SDRAMC_CR - Configuration register*/
88#define CONFIG_SYS_SDRC_CR_VAL \
89 (AT91_SDRAMC_NC_9 | \
90 AT91_SDRAMC_NR_13 | \
91 AT91_SDRAMC_NB_4 | \
92 AT91_SDRAMC_CAS_2 | \
93 AT91_SDRAMC_DBW_32 | \
94 (2 << 8) | /* tWR - Write Recovery Delay */ \
95 (7 << 12) | /* tRC - Row Cycle Delay */ \
96 (2 << 16) | /* tRP - Row Precharge Delay */ \
97 (2 << 20) | /* tRCD - Row to Column Delay */ \
98 (5 << 24) | /* tRAS - Active to Precharge Delay */ \
99 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
100
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200101/* Memory Device Register -> SDRAM */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200102#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
103#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200104#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200105#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200106#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
107#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
108#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
109#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
110#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
111#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
112#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
113#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200114#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200115#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200116#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200117#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
118#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
119#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
120
121/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200122#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300123 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
124 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200125#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300126 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
127 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200128#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300129 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200130#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300131 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
132 AT91_SMC_MODE_DBW_16 | \
133 AT91_SMC_MODE_TDF | \
134 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200135
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200136/* user reset enable */
137#define CONFIG_SYS_RSTC_RMR_VAL \
138 (AT91_RSTC_KEY | \
Asen Dimov20d98c22010-04-19 14:18:43 +0300139 AT91_RSTC_CR_PROCRST | \
140 AT91_RSTC_MR_ERSTL(1) | \
141 AT91_RSTC_MR_ERSTL(2))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200142
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200143/* Disable Watchdog */
144#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300145 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
146 AT91_WDT_MR_WDV(0xfff) | \
147 AT91_WDT_MR_WDDIS | \
148 AT91_WDT_MR_WDD(0xfff))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200149
150#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
151#define CONFIG_SETUP_MEMORY_TAGS 1
152#define CONFIG_INITRD_TAG 1
153
154#undef CONFIG_SKIP_LOWLEVEL_INIT
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200155#define CONFIG_USER_LOWLEVEL_INIT 1
Asen Dimov52b26012011-12-09 10:56:55 +0000156#define CONFIG_BOARD_EARLY_INIT_F
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200157
158/*
159 * Hardware drivers
160 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100161#define CONFIG_AT91_GPIO 1
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200162#define CONFIG_ATMEL_USART 1
Asen Dimov684a5672011-06-08 22:01:16 +0000163#define CONFIG_USART_BASE ATMEL_BASE_DBGU
164#define CONFIG_USART_ID ATMEL_ID_SYS
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200165
166/* LCD */
167#define CONFIG_LCD 1
168#define LCD_BPP LCD_COLOR8
169#define CONFIG_LCD_LOGO 1
170#undef LCD_TEST_PATTERN
171#define CONFIG_LCD_INFO 1
172#define CONFIG_LCD_INFO_BELOW_LOGO 1
173#define CONFIG_SYS_WHITE_ON_BLACK 1
174#define CONFIG_ATMEL_LCD 1
175#define CONFIG_ATMEL_LCD_BGR555 1
176#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
177
178#define CONFIG_LCD_IN_PSRAM 1
179
180/* LED */
181#define CONFIG_AT91_LED
Asen Dimov20d98c22010-04-19 14:18:43 +0300182#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */
183#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200184
185#define CONFIG_BOOTDELAY 3
186
187/*
188 * BOOTP options
189 */
190#define CONFIG_BOOTP_BOOTFILESIZE 1
191#define CONFIG_BOOTP_BOOTPATH 1
192#define CONFIG_BOOTP_GATEWAY 1
193#define CONFIG_BOOTP_HOSTNAME 1
194
195/*
196 * Command line configuration.
197 */
198#include <config_cmd_default.h>
199#undef CONFIG_CMD_BDI
200#undef CONFIG_CMD_IMI
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200201#undef CONFIG_CMD_FPGA
202#undef CONFIG_CMD_LOADS
203#undef CONFIG_CMD_IMLS
204
Asen Dimov6e110d22010-12-12 12:42:09 +0200205#define CONFIG_CMD_CACHE
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200206#define CONFIG_CMD_PING 1
207#define CONFIG_CMD_DHCP 1
208#define CONFIG_CMD_NAND 1
209#define CONFIG_CMD_USB 1
210
211/* SDRAM */
212#define CONFIG_NR_DRAM_BANKS 1
213#define PHYS_SDRAM 0x20000000
214#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
215
216/* DataFlash */
217#define CONFIG_ATMEL_DATAFLASH_SPI
218#define CONFIG_HAS_DATAFLASH 1
219#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
220#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
221#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
222#define AT91_SPI_CLK 15000000
223#define DATAFLASH_TCSS (0x1a << 16)
224#define DATAFLASH_TCHS (0x1 << 24)
225
226/* NOR flash, if populated */
227#define CONFIG_SYS_FLASH_CFI 1
228#define CONFIG_FLASH_CFI_DRIVER 1
229#define PHYS_FLASH_1 0x10000000
230#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
231#define CONFIG_SYS_MAX_FLASH_SECT 256
232#define CONFIG_SYS_MAX_FLASH_BANKS 1
233
234/* NAND flash */
235#ifdef CONFIG_CMD_NAND
236#define CONFIG_NAND_ATMEL
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200237#define CONFIG_SYS_MAX_NAND_DEVICE 1
238#define CONFIG_SYS_NAND_BASE 0x40000000
239#define CONFIG_SYS_NAND_DBW_8 1
240/* our ALE is AD21 */
241#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
242/* our CLE is AD22 */
243#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Asen Dimov20d98c22010-04-19 14:18:43 +0300244#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
245#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200246
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200247#endif
248
249#define CONFIG_CMD_JFFS2 1
250#define CONFIG_JFFS2_CMDLINE 1
251#define CONFIG_JFFS2_NAND 1
252#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
253#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
254#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
255
256/* PSRAM */
257#define PHYS_PSRAM 0x70000000
258#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
Asen Dimov20d98c22010-04-19 14:18:43 +0300259/* Slave EBI1, PSRAM connected */
260#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
261 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
262 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
263 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200264
265/* Ethernet */
266#define CONFIG_MACB 1
267#define CONFIG_RMII 1
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200268#define CONFIG_NET_RETRY_COUNT 20
269#define CONFIG_RESET_PHY_R 1
270
271/* USB */
272#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800273#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200274#define CONFIG_USB_OHCI_NEW 1
275#define CONFIG_DOS_PARTITION 1
276#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
277#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
278#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
279#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
280#define CONFIG_USB_STORAGE 1
281
282#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
283
284#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
285#define CONFIG_SYS_MEMTEST_END 0x23e00000
286
287#define CONFIG_SYS_USE_FLASH 1
288#undef CONFIG_SYS_USE_DATAFLASH
289#undef CONFIG_SYS_USE_NANDFLASH
290
291#ifdef CONFIG_SYS_USE_DATAFLASH
292
293/* bootstrap + u-boot + env + linux in dataflash on CS0 */
294#define CONFIG_ENV_IS_IN_DATAFLASH
295#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
296#define CONFIG_ENV_OFFSET 0x4200
297#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
298#define CONFIG_ENV_SIZE 0x4200
299#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
300#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
301 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200302 "mtdparts=atmel_nand:-(root) "\
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200303 "rw rootfstype=jffs2"
304
305#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
306
307/* bootstrap + u-boot + env + linux in nandflash */
308#define CONFIG_ENV_IS_IN_NAND
309#define CONFIG_ENV_OFFSET 0x60000
310#define CONFIG_ENV_OFFSET_REDUND 0x80000
311#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
312#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
313#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
314 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200315 "mtdparts=atmel_nand:" \
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200316 "128k(bootstrap)ro," \
317 "256k(uboot)ro," \
318 "128k(env1)ro," \
319 "128k(env2)ro," \
320 "2M(linux)," \
321 "-(root) " \
322 "rw rootfstype=jffs2"
323
324#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
325
326#define CONFIG_ENV_IS_IN_FLASH 1
327#define CONFIG_ENV_OFFSET 0x40000
328#define CONFIG_ENV_SECT_SIZE 0x10000
329#define CONFIG_ENV_SIZE 0x10000
330#define CONFIG_ENV_OVERWRITE 1
331
332/* JFFS Partition offset set */
333#define CONFIG_SYS_JFFS2_FIRST_BANK 0
334#define CONFIG_SYS_JFFS2_NUM_BANKS 1
335
336/* 512k reserved for u-boot */
337#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
338
339#define CONFIG_BOOTCOMMAND "run flashboot"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000340#define CONFIG_ROOTPATH "/ronetix/rootfs"
Simon Glass6236fd72013-05-15 06:23:53 +0000341#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200342
343#define CONFIG_CON_ROT "fbcon=rotate:3 "
344#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
345 CONFIG_CON_ROT
346
347#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
348#define MTDPARTS_DEFAULT \
349 "mtdparts=physmap-flash.0:" \
350 "256k(u-boot)ro," \
351 "64k(u-boot-env)ro," \
352 "1408k(kernel)," \
353 "-(rootfs);" \
354 "nand:-(nand)"
355
356#define CONFIG_EXTRA_ENV_SETTINGS \
357 "mtdids=" MTDIDS_DEFAULT "\0" \
358 "mtdparts=" MTDPARTS_DEFAULT "\0" \
359 "partition=nand0,0\0" \
360 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
361 "nfsargs=setenv bootargs root=/dev/nfs rw " \
362 CONFIG_CON_ROT \
363 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
364 "addip=setenv bootargs $(bootargs) " \
365 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
366 ":$(hostname):eth0:off\0" \
367 "ramboot=tftpboot 0x22000000 vmImage;" \
368 "run ramargs;run addip;bootm 22000000\0" \
369 "nfsboot=tftpboot 0x22000000 vmImage;" \
370 "run nfsargs;run addip;bootm 22000000\0" \
371 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
372 ""
373
374#else
375#error "Undefined memory device"
376#endif
377
378#define CONFIG_BAUDRATE 115200
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200379
380#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
381#define CONFIG_SYS_CBSIZE 256
382#define CONFIG_SYS_MAXARGS 16
383#define CONFIG_SYS_PBSIZE \
384 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
385#define CONFIG_SYS_LONGHELP 1
386#define CONFIG_CMDLINE_EDITING 1
387
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200388/*
389 * Size of malloc() pool
390 */
391#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200392
Asen Dimov9a2a05a2010-12-12 12:41:59 +0200393#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
394#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
395 GENERATED_GBL_DATA_SIZE)
396
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200397#endif