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Bo Shen3225f342013-05-12 22:40:54 +00001/*
2 * Configuation settings for the SAMA5D3xEK board.
3 *
4 * Copyright (C) 2012 - 2013 Atmel
5 *
6 * based on at91sam9m10g45ek.h by:
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Bo Shen3225f342013-05-12 22:40:54 +000011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#include <asm/hardware.h>
17
18#define CONFIG_SYS_TEXT_BASE 0x26f00000
19
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
22#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Bo Shen3225f342013-05-12 22:40:54 +000023
24#define CONFIG_AT91FAMILY
25#define CONFIG_ARCH_CPU_INIT
26
27#define CONFIG_SKIP_LOWLEVEL_INIT
28#define CONFIG_BOARD_EARLY_INIT_F
29#define CONFIG_DISPLAY_CPUINFO
30
31#define CONFIG_CMD_BOOTZ
32#define CONFIG_OF_LIBFDT /* Device Tree support */
33
34/* general purpose I/O */
35#define CONFIG_AT91_GPIO
36
37/* serial console */
38#define CONFIG_ATMEL_USART
39#define CONFIG_USART_BASE ATMEL_BASE_DBGU
40#define CONFIG_USART_ID ATMEL_ID_DBGU
41
42/*
43 * This needs to be defined for the OHCI code to work but it is defined as
44 * ATMEL_ID_UHPHS in the CPU specific header files.
45 */
46#define ATMEL_ID_UHP ATMEL_ID_UHPHS
47
48/*
49 * Specify the clock enable bit in the PMC_SCER register.
50 */
51#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
52
53/* LCD */
54#define CONFIG_LCD
55#define LCD_BPP LCD_COLOR16
56#define LCD_OUTPUT_BPP 24
57#define CONFIG_LCD_LOGO
Bo Shen3225f342013-05-12 22:40:54 +000058#define CONFIG_LCD_INFO
59#define CONFIG_LCD_INFO_BELOW_LOGO
60#define CONFIG_SYS_WHITE_ON_BLACK
61#define CONFIG_ATMEL_HLCD
62#define CONFIG_ATMEL_LCD_RGB565
63#define CONFIG_SYS_CONSOLE_IS_IN_ENV
64
65/* board specific (not enough SRAM) */
66#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
67
68#define CONFIG_BOOTDELAY 3
69
70/*
71 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78/* No NOR flash */
79#define CONFIG_SYS_NO_FLASH
80
81/*
82 * Command line configuration.
83 */
84#include <config_cmd_default.h>
85#undef CONFIG_CMD_FPGA
86#undef CONFIG_CMD_IMI
87#undef CONFIG_CMD_LOADS
88#define CONFIG_CMD_PING
89#define CONFIG_CMD_DHCP
90
91/* SDRAM */
92#define CONFIG_NR_DRAM_BANKS 1
93#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
94#define CONFIG_SYS_SDRAM_SIZE 0x20000000
95
96#define CONFIG_SYS_INIT_SP_ADDR \
97 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
98
99/* SerialFlash */
100#define CONFIG_CMD_SF
101
102#ifdef CONFIG_CMD_SF
103#define CONFIG_ATMEL_SPI
104#define CONFIG_SPI_FLASH
105#define CONFIG_SPI_FLASH_ATMEL
106#define CONFIG_SF_DEFAULT_SPEED 30000000
107#endif
108
109/* NAND flash */
110#define CONFIG_CMD_NAND
111
112#ifdef CONFIG_CMD_NAND
Bo Shen3225f342013-05-12 22:40:54 +0000113#define CONFIG_NAND_ATMEL
114#define CONFIG_SYS_MAX_NAND_DEVICE 1
115#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
116/* our ALE is AD21 */
117#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
118/* our CLE is AD22 */
119#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
120#define CONFIG_SYS_NAND_ONFI_DETECTION
121/* PMECC & PMERRLOC */
122#define CONFIG_ATMEL_NAND_HWECC
123#define CONFIG_ATMEL_NAND_HW_PMECC
124#define CONFIG_PMECC_CAP 4
125#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen3225f342013-05-12 22:40:54 +0000126#define CONFIG_CMD_NAND_TRIMFFS
127#endif
128
129/* Ethernet Hardware */
130#define CONFIG_MACB
131#define CONFIG_RMII
Bo Shen3225f342013-05-12 22:40:54 +0000132#define CONFIG_NET_RETRY_COUNT 20
133#define CONFIG_MACB_SEARCH_PHY
Bo Shene08d6f32013-06-26 10:11:06 +0800134#define CONFIG_RGMII
135#define CONFIG_CMD_MII
136#define CONFIG_PHYLIB
137#define CONFIG_PHY_MICREL
138#define CONFIG_PHY_MICREL_KSZ9021
Bo Shen3225f342013-05-12 22:40:54 +0000139
140/* MMC */
141#define CONFIG_CMD_MMC
142
143#ifdef CONFIG_CMD_MMC
144#define CONFIG_MMC
145#define CONFIG_GENERIC_MMC
146#define CONFIG_GENERIC_ATMEL_MCI
147#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
148#endif
149
150/* USB */
151#define CONFIG_CMD_USB
152
153#ifdef CONFIG_CMD_USB
154#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800155#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen3225f342013-05-12 22:40:54 +0000156#define CONFIG_USB_OHCI_NEW
157#define CONFIG_SYS_USB_OHCI_CPU_INIT
158#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
159#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
160#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
161#define CONFIG_DOS_PARTITION
162#define CONFIG_USB_STORAGE
163#endif
164
Bo Shen3668ce32013-09-11 18:24:51 +0800165/* USB device */
166#define CONFIG_USB_GADGET
167#define CONFIG_USB_GADGET_DUALSPEED
168#define CONFIG_USB_GADGET_ATMEL_USBA
169#define CONFIG_USB_ETHER
170#define CONFIG_USB_ETH_RNDIS
171#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
172
Bo Shen3225f342013-05-12 22:40:54 +0000173#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
174#define CONFIG_CMD_FAT
175#endif
176
177#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
178
179#ifdef CONFIG_SYS_USE_SERIALFLASH
180/* bootstrap + u-boot + env + linux in serial flash */
181#define CONFIG_ENV_IS_IN_SPI_FLASH
182#define CONFIG_ENV_OFFSET 0x5000
183#define CONFIG_ENV_SIZE 0x3000
184#define CONFIG_ENV_SECT_SIZE 0x1000
185#define CONFIG_BOOTCOMMAND "sf probe 0; " \
186 "sf read 0x22000000 0x42000 0x300000; " \
187 "bootm 0x22000000"
188#elif CONFIG_SYS_USE_NANDFLASH
189/* bootstrap + u-boot + env in nandflash */
190#define CONFIG_ENV_IS_IN_NAND
191#define CONFIG_ENV_OFFSET 0xc0000
192#define CONFIG_ENV_OFFSET_REDUND 0x100000
193#define CONFIG_ENV_SIZE 0x20000
194#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
195 "nand read 0x22000000 0x200000 0x600000;" \
196 "bootm 0x22000000 - 0x21000000"
197#elif CONFIG_SYS_USE_MMC
198/* bootstrap + u-boot + env in sd card */
199#define CONFIG_ENV_IS_IN_MMC
200#define CONFIG_ENV_OFFSET 0x2000
201#define CONFIG_ENV_SIZE 0x1000
202#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
203 "fatload mmc 0:1 0x22000000 uImage; " \
204 "bootm 0x22000000 - 0x21000000"
205#define CONFIG_SYS_MMC_ENV_DEV 0
206#else
Bo Shena4c79b32013-08-11 14:26:20 +0000207#define CONFIG_ENV_IS_NOWHERE
Bo Shen3225f342013-05-12 22:40:54 +0000208#endif
209
210#ifdef CONFIG_SYS_USE_MMC
211#define CONFIG_BOOTARGS \
212 "console=ttyS0,115200 earlyprintk " \
213 "root=/dev/mmcblk0p2 rw rootwait"
214#else
215#define CONFIG_BOOTARGS \
216 "console=ttyS0,115200 earlyprintk " \
217 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
218 "256K(env),256k(evn_redundent),256k(spare)," \
219 "512k(dtb),6M(kernel)ro,-(rootfs) " \
220 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
221#endif
222
223#define CONFIG_BAUDRATE 115200
224
225#define CONFIG_SYS_PROMPT "U-Boot> "
226#define CONFIG_SYS_CBSIZE 256
227#define CONFIG_SYS_MAXARGS 16
228#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
229 sizeof(CONFIG_SYS_PROMPT) + 16)
230#define CONFIG_SYS_LONGHELP
231#define CONFIG_CMDLINE_EDITING
232#define CONFIG_AUTO_COMPLETE
233#define CONFIG_SYS_HUSH_PARSER
234
235/* Size of malloc() pool */
236#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
237
238#endif