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wdenk4ec3a7f2004-09-28 16:44:41 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2004-2005
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
wdenk4ec3a7f2004-09-28 16:44:41 +00005 * (C) Copyright 2004
6 * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
7 *
8 * (C) Copyright 2002
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * Configuation settings for the xaeniax board.
16 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020017 * SPDX-License-Identifier: GPL-2.0+
wdenk4ec3a7f2004-09-28 16:44:41 +000018 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
wdenk4ec3a7f2004-09-28 16:44:41 +000024 * High Level Configuration Options
25 * (easy to change)
26 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010027#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */
wdenk4ec3a7f2004-09-28 16:44:41 +000028#define CONFIG_XAENIAX 1 /* on a xaeniax board */
Marek Vasut1123d412010-10-20 21:54:19 +020029#define CONFIG_SYS_TEXT_BASE 0x0
wdenk4ec3a7f2004-09-28 16:44:41 +000030
Helmut Raiger9660e442011-10-20 04:19:47 +000031#define CONFIG_BOARD_LATE_INIT
wdenk4ec3a7f2004-09-28 16:44:41 +000032
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020033/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000034#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020035
wdenk4ec3a7f2004-09-28 16:44:41 +000036/*
37 * select serial console configuration
38 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020039#define CONFIG_PXA_SERIAL
wdenk4ec3a7f2004-09-28 16:44:41 +000040#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */
Marek Vasutce6971c2012-09-12 12:36:25 +020041#define CONFIG_CONS_INDEX 4
wdenk4ec3a7f2004-09-28 16:44:41 +000042
43/* allow to overwrite serial and ethaddr */
44#define CONFIG_ENV_OVERWRITE
45
wdenk414eec32005-04-02 22:37:54 +000046#define CONFIG_TIMESTAMP /* Print image info with timestamp */
47
wdenk4ec3a7f2004-09-28 16:44:41 +000048#define CONFIG_BAUDRATE 115200
49
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050050/*
Jon Loeliger079a1362007-07-10 10:12:10 -050051 * BOOTP options
52 */
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
58
59/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050060 * Command line configuration.
61 */
62#include <config_cmd_default.h>
63
64#define CONFIG_CMD_DHCP
65#define CONFIG_CMD_DIAG
66#define CONFIG_CMD_NFS
67#define CONFIG_CMD_SDRAM
68#define CONFIG_CMD_SNTP
69
70#undef CONFIG_CMD_DTT
71
wdenk4ec3a7f2004-09-28 16:44:41 +000072
73#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
74#define CONFIG_NETMASK 255.255.255.0
75#define CONFIG_IPADDR 192.168.68.201
76#define CONFIG_SERVERIP 192.168.68.62
77
78#define CONFIG_BOOTDELAY 3
79#define CONFIG_BOOTCOMMAND "bootm 0x00100000"
80#define CONFIG_BOOTARGS "console=ttyS1,115200"
wdenk14699a22004-10-19 22:17:51 +000081#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020082#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk14699a22004-10-19 22:17:51 +000083#define CONFIG_INITRD_TAG 1
wdenk4ec3a7f2004-09-28 16:44:41 +000084
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050085#if defined(CONFIG_CMD_KGDB)
wdenk4ec3a7f2004-09-28 16:44:41 +000086#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
87#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
88#endif
89
90/*
91 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
92 * used for the RAM copy of the uboot code
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk4ec3a7f2004-09-28 16:44:41 +000095
96/*
97 * Miscellaneous configurable options
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LONGHELP /* undef to save memory */
100#define CONFIG_SYS_HUSH_PARSER 1
wdenk4ec3a7f2004-09-28 16:44:41 +0000101
wdenk4ec3a7f2004-09-28 16:44:41 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#ifdef CONFIG_SYS_HUSH_PARSER
104#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */
wdenk4ec3a7f2004-09-28 16:44:41 +0000105#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */
wdenk4ec3a7f2004-09-28 16:44:41 +0000107#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
110#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
112#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenk4ec3a7f2004-09-28 16:44:41 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
115#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenk4ec3a7f2004-09-28 16:44:41 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
wdenk4ec3a7f2004-09-28 16:44:41 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
wdenk4ec3a7f2004-09-28 16:44:41 +0000120
121/*
122 * Physical Memory Map
123 */
124#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */
125#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
126#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
127#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
128#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
129#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
130#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
131#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
132#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
133
134#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
135#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
136#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
137#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
138#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_DRAM_BASE 0xa0000000
141#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenk4ec3a7f2004-09-28 16:44:41 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk4ec3a7f2004-09-28 16:44:41 +0000144
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200145#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut00d5ec92011-11-26 12:04:11 +0100146#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200147
wdenk4ec3a7f2004-09-28 16:44:41 +0000148/*
149 * FLASH and environment organization
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
152#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenk4ec3a7f2004-09-28 16:44:41 +0000153
154/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
156#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk4ec3a7f2004-09-28 16:44:41 +0000157
158/* FIXME */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200159#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200160#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */
161#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenk4ec3a7f2004-09-28 16:44:41 +0000162
163/*
wdenk4ec3a7f2004-09-28 16:44:41 +0000164 * SMSC91C111 Network Card
165 */
Ben Warren7194ab82009-10-04 22:37:03 -0700166#define CONFIG_SMC91111 1
wdenk1f6d4252004-11-02 13:00:33 +0000167#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */
wdenk4ec3a7f2004-09-28 16:44:41 +0000168#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
169#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
170#undef CONFIG_SHOW_ACTIVITY
171#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
172
173/*
174 * GPIO settings
175 */
176
177/*
178 * GP05 == nUSBReset is 1
179 * GP10 == CFReset is 1
180 * GP13 == nCFDataEnable is 1
181 * GP14 == nCFAddrEnable is 1
182 * GP15 == nCS1 is 1
183 * GP21 == ComBrdReset is 1
184 * GP24 == SFRM is 1
185 * GP25 == TXD is 1
186 * GP31 == SYNC is 1
187 * GP33 == nCS5 is 1
188 * GP39 == FFTXD is 1
189 * GP41 == RTS is 1
190 * GP43 == BTTXD is 1
191 * GP45 == BTRTS is 1
192 * GP47 == TXD is 1
193 * GP48 == nPOE is 1
194 * GP49 == nPWE is 1
195 * GP50 == nPIOR is 1
196 * GP51 == nPIOW is 1
197 * GP52 == nPCE[1] is 1
198 * GP53 == nPCE[2] is 1
199 * GP54 == nPSKTSEL is 1
200 * GP55 == nPREG is 1
201 * GP78 == nCS2 is 1
202 * GP79 == nCS3 is 1
203 * GP80 == nCS4 is 1
204 * GP82 == NSSPSFRM is 1
205 * GP83 == NSSPTXD is 1
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_GPSR0_VAL 0x8320E420
208#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82
209#define CONFIG_SYS_GPSR2_VAL 0x000DC000
wdenk4ec3a7f2004-09-28 16:44:41 +0000210
211/*
212 * GP03 == LANReset is 0
213 * GP06 == USBWakeUp is 0
214 * GP11 == USBControl is 0
215 * GP12 == Buzzer is 0
216 * GP16 == PWM0 is 0
217 * GP17 == PWM1 is 0
218 * GP23 == SCLK is 0
219 * GP30 == SDATA_OUT is 0
220 * GP81 == NSSPCLK is 0
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_GPCR0_VAL 0x40C31848
223#define CONFIG_SYS_GPCR1_VAL 0x00000000
224#define CONFIG_SYS_GPCR2_VAL 0x00020000
wdenk4ec3a7f2004-09-28 16:44:41 +0000225
226/*
227 * GP00 == CPUWakeUpUSB is input
228 * GP01 == GP reset is input
229 * GP02 == LANInterrupt is input
230 * GP03 == LANReset is output
231 * GP04 == USBInterrupt is input
232 * GP05 == nUSBReset is output
233 * GP06 == USBWakeUp is output
234 * GP07 == CFReady/nBusy is input
235 * GP08 == nCFCardDetect1 is input
236 * GP09 == nCFCardDetect2 is input
237 * GP10 == nCFReset is output
238 * GP11 == USBControl is output
239 * GP12 == Buzzer is output
240 * GP13 == CFDataEnable is output
241 * GP14 == CFAddressEnable is output
242 * GP15 == nCS1 is output
243 * GP16 == PWM0 is output
244 * GP17 == PWM1 is output
245 * GP18 == RDY is input
246 * GP19 == ReaderReady is input
247 * GP20 == ReaderReset is input
248 * GP21 == ComBrdReset is output
249 * GP23 == SCLK is output
250 * GP24 == SFRM is output
251 * GP25 == TXD is output
252 * GP26 == RXD is input
253 * GP27 == EXTCLK is input
254 * GP28 == BITCLK is output
255 * GP29 == SDATA_IN0 is input
256 * GP30 == SDATA_OUT is output
257 * GP31 == SYNC is output
258 * GP32 == SYSSCLK is output
259 * GP33 == nCS5 is output
260 * GP34 == FFRXD is input
261 * GP35 == CTS is input
262 * GP36 == DCD is input
263 * GP37 == DSR is input
264 * GP38 == RI is input
265 * GP39 == FFTXD is output
266 * GP40 == DTR is output
267 * GP41 == RTS is output
268 * GP42 == BTRXD is input
269 * GP43 == BTTXD is output
270 * GP44 == BTCTS is input
271 * GP45 == BTRTS is output
272 * GP46 == RXD is input
273 * GP47 == TXD is output
274 * GP48 == nPOE is output
275 * GP49 == nPWE is output
276 * GP50 == nPIOR is output
277 * GP51 == nPIOW is output
278 * GP52 == nPCE[1] is output
279 * GP53 == nPCE[2] is output
280 * GP54 == nPSKTSEL is output
281 * GP55 == nPREG is output
282 * GP56 == nPWAIT is input
283 * GP57 == nPIOS16 is input
284 * GP58 == LDD[0] is output
285 * GP59 == LDD[1] is output
286 * GP60 == LDD[2] is output
287 * GP61 == LDD[3] is output
288 * GP62 == LDD[4] is output
289 * GP63 == LDD[5] is output
290 * GP64 == LDD[6] is output
291 * GP65 == LDD[7] is output
292 * GP66 == LDD[8] is output
293 * GP67 == LDD[9] is output
294 * GP68 == LDD[10] is output
295 * GP69 == LDD[11] is output
296 * GP70 == LDD[12] is output
297 * GP71 == LDD[13] is output
298 * GP72 == LDD[14] is output
299 * GP73 == LDD[15] is output
300 * GP74 == LCD_FCLK is output
301 * GP75 == LCD_LCLK is output
302 * GP76 == LCD_PCLK is output
303 * GP77 == LCD_ACBIAS is output
304 * GP78 == nCS2 is output
305 * GP79 == nCS3 is output
306 * GP80 == nCS4 is output
307 * GP81 == NSSPCLK is output
308 * GP82 == NSSPSFRM is output
309 * GP83 == NSSPTXD is output
310 * GP84 == NSSPRXD is input
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68
313#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83
314#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF
wdenk4ec3a7f2004-09-28 16:44:41 +0000315
316/*
317 * GP01 == GP reset is AF01
318 * GP15 == nCS1 is AF10
319 * GP16 == PWM0 is AF10
320 * GP17 == PWM1 is AF10
321 * GP18 == RDY is AF01
322 * GP23 == SCLK is AF10
323 * GP24 == SFRM is AF10
324 * GP25 == TXD is AF10
325 * GP26 == RXD is AF01
326 * GP27 == EXTCLK is AF01
327 * GP28 == BITCLK is AF01
328 * GP29 == SDATA_IN0 is AF10
329 * GP30 == SDATA_OUT is AF01
330 * GP31 == SYNC is AF01
331 * GP32 == SYSCLK is AF01
332 * GP33 == nCS5 is AF10
333 * GP34 == FFRXD is AF01
334 * GP35 == CTS is AF01
335 * GP36 == DCD is AF01
336 * GP37 == DSR is AF01
337 * GP38 == RI is AF01
338 * GP39 == FFTXD is AF10
339 * GP40 == DTR is AF10
340 * GP41 == RTS is AF10
341 * GP42 == BTRXD is AF01
342 * GP43 == BTTXD is AF10
343 * GP44 == BTCTS is AF01
344 * GP45 == BTRTS is AF10
345 * GP46 == RXD is AF10
346 * GP47 == TXD is AF01
347 * GP48 == nPOE is AF10
348 * GP49 == nPWE is AF10
349 * GP50 == nPIOR is AF10
350 * GP51 == nPIOW is AF10
351 * GP52 == nPCE[1] is AF10
352 * GP53 == nPCE[2] is AF10
353 * GP54 == nPSKTSEL is AF10
354 * GP55 == nPREG is AF10
355 * GP56 == nPWAIT is AF01
356 * GP57 == nPIOS16 is AF01
357 * GP58 == LDD[0] is AF10
358 * GP59 == LDD[1] is AF10
359 * GP60 == LDD[2] is AF10
360 * GP61 == LDD[3] is AF10
361 * GP62 == LDD[4] is AF10
362 * GP63 == LDD[5] is AF10
363 * GP64 == LDD[6] is AF10
364 * GP65 == LDD[7] is AF10
365 * GP66 == LDD[8] is AF10
366 * GP67 == LDD[9] is AF10
367 * GP68 == LDD[10] is AF10
368 * GP69 == LDD[11] is AF10
369 * GP70 == LDD[12] is AF10
370 * GP71 == LDD[13] is AF10
371 * GP72 == LDD[14] is AF10
372 * GP73 == LDD[15] is AF10
373 * GP74 == LCD_FCLK is AF10
374 * GP75 == LCD_LCLK is AF10
375 * GP76 == LCD_PCLK is AF10
376 * GP77 == LCD_ACBIAS is AF10
377 * GP78 == nCS2 is AF10
378 * GP79 == nCS3 is AF10
379 * GP80 == nCS4 is AF10
380 * GP81 == NSSPCLK is AF01
381 * GP82 == NSSPSFRM is AF01
382 * GP83 == NSSPTXD is AF01
383 * GP84 == NSSPRXD is AF10
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
386#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A
387#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559
388#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
389#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
390#define CONFIG_SYS_GAFR2_U_VAL 0x00000256
wdenk4ec3a7f2004-09-28 16:44:41 +0000391
392/*
393 * clock settings
394 */
395/* RDH = 1
396 * PH = 0
397 * VFS = 0
398 * BFS = 0
399 * SSS = 0
400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_PSSR_VAL 0x00000030
wdenk4ec3a7f2004-09-28 16:44:41 +0000402
Marek Vasut1123d412010-10-20 21:54:19 +0200403#define CONFIG_SYS_CKEN 0x00000080 /* */
404#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
405#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
wdenk4ec3a7f2004-09-28 16:44:41 +0000406
407
408/*
409 * Memory settings
410 *
411 * This is the configuration for nCS0/1 -> flash banks
412 * configuration for nCS1 :
413 * [31] 0 -
414 * [30:28] 000 -
415 * [27:24] 0000 -
416 * [23:20] 0000 -
417 * [19] 0 -
418 * [18:16] 000 -
419 * configuration for nCS0:
420 * [15] 0 - Slower Device
421 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
422 * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
423 * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
424 * [03] 0 - 32 Bit bus width
425 * [02:00] 010 - burst OF 4 ROM or FLASH
426*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_MSC0_VAL 0x000023D2
wdenk4ec3a7f2004-09-28 16:44:41 +0000428
429/* This is the configuration for nCS2/3 -> USB controller, LAN
430 * configuration for nCS3: LAN
431 * [31] 0 - Slower Device
432 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
433 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
434 * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
435 * [19] 0 - 32 Bit bus width
436 * [18:16] 100 - variable latency I/O
437 * configuration for nCS2: USB
438 * [15] 1 - Faster Device
439 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
440 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
441 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
Wolfgang Denk452f6742005-08-04 19:45:01 +0200442 * [03] 1 - 16 Bit bus width
wdenk4ec3a7f2004-09-28 16:44:41 +0000443 * [02:00] 100 - variable latency I/O
444 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_MSC1_VAL 0x1224A26C
wdenk4ec3a7f2004-09-28 16:44:41 +0000446
447/* This is the configuration for nCS4/5 -> LAN
448 * configuration for nCS5:
449 * [31] 0 -
450 * [30:28] 000 -
451 * [27:24] 0000 -
452 * [23:20] 0000 -
453 * [19] 0 -
454 * [18:16] 000 -
455 * configuration for nCS4: LAN
456 * [15] 1 - Faster Device
457 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
458 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
459 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
460 * [03] 0 - 32 Bit bus width
461 * [02:00] 100 - variable latency I/O
462 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_MSC2_VAL 0x00001224
wdenk4ec3a7f2004-09-28 16:44:41 +0000464
465/* MDCNFG: SDRAM Configuration Register
466 *
467 * [31:29] 000 - reserved
468 * [28] 0 - no SA1111 compatiblity mode
469 * [27] 0 - latch return data with return clock
470 * [26] 0 - alternate addressing for pair 2/3
471 * [25:24] 00 - timings
472 * [23] 0 - internal banks in lower partition 2/3 (not used)
473 * [22:21] 00 - row address bits for partition 2/3 (not used)
474 * [20:19] 00 - column address bits for partition 2/3 (not used)
475 * [18] 0 - SDRAM partition 2/3 width is 32 bit
476 * [17] 0 - SDRAM partition 3 disabled
477 * [16] 0 - SDRAM partition 2 disabled
478 * [15:13] 000 - reserved
479 * [12] 0 - no SA1111 compatiblity mode
480 * [11] 1 - latch return data with return clock
481 * [10] 0 - no alternate addressing for pair 0/1
482 * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
483 * [7] 1 - 4 internal banks in lower partition pair
484 * [06:05] 10 - 13 row address bits for partition 0/1
485 * [04:03] 01 - 9 column address bits for partition 0/1
486 * [02] 0 - SDRAM partition 0/1 width is 32 bit
487 * [01] 0 - disable SDRAM partition 1
488 * [00] 1 - enable SDRAM partition 0
489 */
490/* use the configuration above but disable partition 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9
wdenk4ec3a7f2004-09-28 16:44:41 +0000492
493/* MDREFR: SDRAM Refresh Control Register
494 *
495 * [32:26] 0 - reserved
496 * [25] 0 - K2FREE: not free running
497 * [24] 0 - K1FREE: not free running
498 * [23] 0 - K0FREE: not free running
499 * [22] 0 - SLFRSH: self refresh disabled
500 * [21] 0 - reserved
501 * [20] 1 - APD: auto power down
502 * [19] 0 - K2DB2: SDCLK2 is MemClk
503 * [18] 0 - K2RUN: disable SDCLK2
504 * [17] 0 - K1DB2: SDCLK1 is MemClk
505 * [16] 1 - K1RUN: enable SDCLK1
506 * [15] 1 - E1PIN: SDRAM clock enable
507 * [14] 0 - K0DB2: SDCLK0 is MemClk
508 * [13] 0 - K0RUN: disable SDCLK0
509 * [12] 0 - E0PIN: disable SDCKE0
510 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
511 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */
wdenk4ec3a7f2004-09-28 16:44:41 +0000513
514/* MDMRS: Mode Register Set Configuration Register
515 *
516 * [31] 0 - reserved
517 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
518 * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used)
519 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
520 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
521 * [15] 0 - reserved
522 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
523 * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency.
524 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
525 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
526 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_MDMRS_VAL 0x00320032
wdenk4ec3a7f2004-09-28 16:44:41 +0000528
Marek Vasut1123d412010-10-20 21:54:19 +0200529#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
530#define CONFIG_SYS_SXCNFG_VAL 0x00000000
531
wdenk4ec3a7f2004-09-28 16:44:41 +0000532/*
533 * PCMCIA and CF Interfaces
534 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_MECR_VAL 0x00000000
536#define CONFIG_SYS_MCMEM0_VAL 0x00010504
537#define CONFIG_SYS_MCMEM1_VAL 0x00010504
538#define CONFIG_SYS_MCATT0_VAL 0x00010504
539#define CONFIG_SYS_MCATT1_VAL 0x00010504
540#define CONFIG_SYS_MCIO0_VAL 0x00004715
541#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenk4ec3a7f2004-09-28 16:44:41 +0000542
543
544#endif /* __CONFIG_H */