Wolfgang Denk | ac7eb8a | 2005-09-14 23:53:32 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
| 3 | * |
| 4 | * Configuation settings for the TI OMAP NetStar board. |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef __CONFIG_H |
| 26 | #define __CONFIG_H |
| 27 | |
| 28 | #include <configs/omap1510.h> |
| 29 | |
| 30 | /* |
| 31 | * High Level Configuration Options |
| 32 | * (easy to change) |
| 33 | */ |
| 34 | #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
| 35 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
| 36 | #define CONFIG_OMAP1510 1 /* which is in a 5910 */ |
| 37 | |
| 38 | /* Input clock of PLL */ |
| 39 | #define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ |
| 40 | #define CONFIG_XTAL_FREQ 12000000 |
| 41 | |
| 42 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| 43 | |
| 44 | #define CONFIG_MISC_INIT_R /* There is nothing to really init */ |
| 45 | #define BOARD_LATE_INIT /* but we flash the LEDs here */ |
| 46 | |
| 47 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 48 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 49 | #define CONFIG_INITRD_TAG 1 |
| 50 | |
| 51 | #define CFG_DEVICE_NULLDEV 1 /* enable null device */ |
| 52 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
| 53 | |
| 54 | /* |
| 55 | * Physical Memory Map |
| 56 | */ |
| 57 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 58 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
| 59 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 60 | |
| 61 | /* |
| 62 | * FLASH organization |
| 63 | */ |
| 64 | #define CFG_FLASH_BASE PHYS_FLASH_1 |
| 65 | #define CFG_MAX_FLASH_BANKS 1 |
| 66 | #if (PHYS_SDRAM_1_SIZE == SZ_32M) |
| 67 | /*#if 1*/ |
| 68 | #define CFG_FLASH_CFI /* Flash is CFI conformant */ |
| 69 | #define CFG_FLASH_CFI_DRIVER /* Use the common driver */ |
| 70 | #define CFG_FLASH_EMPTY_INFO |
| 71 | #define CFG_MAX_FLASH_SECT 128 |
| 72 | #else |
| 73 | #define PHYS_FLASH_1_SIZE SZ_1M |
| 74 | #define CFG_MAX_FLASH_SECT 19 |
| 75 | #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */ |
| 76 | #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) |
| 77 | #endif |
| 78 | |
| 79 | #define CFG_MONITOR_BASE PHYS_FLASH_1 |
| 80 | #define CFG_MONITOR_LEN SZ_256K |
| 81 | |
| 82 | /* |
| 83 | * Environment settings |
| 84 | */ |
| 85 | #define CFG_ENV_IS_IN_FLASH |
| 86 | #define ENV_IS_SOLITARY |
| 87 | #define CFG_ENV_ADDR 0x4000 |
| 88 | #define CFG_ENV_SIZE SZ_8K |
| 89 | #define CFG_ENV_SECT_SIZE SZ_8K |
| 90 | #define CFG_ENV_ADDR_REDUND 0x6000 |
| 91 | #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE |
| 92 | #define CONFIG_ENV_OVERWRITE |
| 93 | |
| 94 | /* |
| 95 | * Size of malloc() pool |
| 96 | */ |
| 97 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 98 | /* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/ |
| 99 | #define CFG_MALLOC_LEN SZ_4M |
| 100 | |
| 101 | /* |
| 102 | * The stack size is set up in start.S using the settings below |
| 103 | */ |
| 104 | /* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */ |
| 105 | #define CONFIG_STACKSIZE SZ_1M /* regular stack */ |
| 106 | |
| 107 | /* |
| 108 | * Hardware drivers |
| 109 | */ |
| 110 | #define CONFIG_DRIVER_SMC91111 |
| 111 | #define CONFIG_SMC91111_BASE 0x04000300 |
| 112 | |
| 113 | /* |
| 114 | * NS16550 Configuration |
| 115 | */ |
| 116 | #define CFG_NS16550 |
| 117 | #define CFG_NS16550_SERIAL |
| 118 | #define CFG_NS16550_REG_SIZE (-4) |
| 119 | #define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ |
| 120 | #define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ |
| 121 | |
| 122 | #define CONFIG_CONS_INDEX 1 |
| 123 | #define CONFIG_BAUDRATE 115200 |
| 124 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 125 | |
| 126 | /*#define CONFIG_SKIP_RELOCATE_UBOOT*/ |
| 127 | /*#define CONFIG_SKIP_LOWLEVEL_INIT */ |
| 128 | |
| 129 | /* |
| 130 | * NAND flash |
| 131 | */ |
| 132 | #define CFG_MAX_NAND_DEVICE 1 |
| 133 | #define CFG_NAND_BASE 0x04000000 + (2 << 23) |
| 134 | #define CONFIG_NEW_NAND_CODE |
| 135 | |
| 136 | /* |
| 137 | * JFFS2 partitions (mtdparts command line support) |
| 138 | */ |
| 139 | #define CONFIG_JFFS2_CMDLINE |
| 140 | #define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" |
| 141 | #define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)" |
| 142 | |
| 143 | #if 0 |
| 144 | #define CONFIG_COMMANDS (CFG_CMD_BDI | \ |
| 145 | CFG_CMD_BOOTD | \ |
| 146 | CFG_CMD_DHCP | \ |
| 147 | CFG_CMD_ENV | \ |
| 148 | CFG_CMD_FLASH | \ |
| 149 | CFG_CMD_IMI | \ |
| 150 | CFG_CMD_LOADB | \ |
| 151 | CFG_CMD_NET | \ |
| 152 | CFG_CMD_MEMORY | \ |
| 153 | CFG_CMD_PING | \ |
| 154 | CFG_CMD_RUN) |
| 155 | |
| 156 | #else |
| 157 | #define CONFIG_COMMANDS (CFG_CMD_BDI | \ |
| 158 | CFG_CMD_BOOTD | \ |
| 159 | CFG_CMD_DHCP | \ |
| 160 | CFG_CMD_ENV | \ |
| 161 | CFG_CMD_FLASH | \ |
| 162 | CFG_CMD_NAND | \ |
| 163 | CFG_CMD_IMI | \ |
| 164 | CFG_CMD_JFFS2 | \ |
| 165 | CFG_CMD_LOADB | \ |
| 166 | CFG_CMD_NET | \ |
| 167 | CFG_CMD_MEMORY | \ |
| 168 | CFG_CMD_PING | \ |
| 169 | CFG_CMD_RUN) |
| 170 | |
| 171 | #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ |
| 172 | #endif |
| 173 | |
| 174 | #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
| 175 | #define CONFIG_LOOPW |
| 176 | |
| 177 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 178 | #include <cmd_confdefs.h> |
| 179 | |
| 180 | #define CONFIG_BOOTDELAY 3 |
| 181 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ |
| 182 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 183 | #define CFG_AUTOLOAD "n" /* No autoload */ |
| 184 | #define CONFIG_BOOTCOMMAND "run nboot" |
| 185 | #define CONFIG_PREBOOT "run setup" |
| 186 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 187 | "setup=setenv bootargs console=ttyS0,$baudrate " \ |
| 188 | "$mtdparts\0" \ |
| 189 | "ospart=0\0" \ |
| 190 | "setpart=" \ |
| 191 | "if test -n $swapos; then " \ |
| 192 | "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\ |
| 193 | "setenv swapos; saveenv; " \ |
| 194 | "else " \ |
| 195 | "chpart nand0,$ospart; " \ |
| 196 | "fi\0" \ |
| 197 | "nfsargs=setenv bootargs $bootargs " \ |
| 198 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ |
| 199 | "nfsroot=$rootpath root=/dev/nfs\0" \ |
| 200 | "flashargs=run setpart;setenv bootargs $bootargs " \ |
| 201 | "root=/dev/mtdblock$partition ro " \ |
| 202 | "rootfstype=jffs2\0" \ |
| 203 | "initrdargs=setenv bootargs $bootargs " \ |
| 204 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ |
| 205 | "iboot=bootp;run initrdargs;tftp;bootm\0" \ |
| 206 | "fboot=run flashargs;fsload /boot/uImage;bootm\0" \ |
| 207 | "nboot=bootp;run nfsargs;tftp;bootm\0" |
| 208 | |
| 209 | #if 0 /* feel free to disable for development */ |
| 210 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ |
| 211 | #define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n" |
| 212 | #define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ |
| 213 | #define CONFIG_BOOT_RETRY_TIME 30 |
| 214 | #endif |
| 215 | |
| 216 | /* |
| 217 | * Miscellaneous configurable options |
| 218 | */ |
| 219 | #define CFG_LONGHELP /* undef to save memory */ |
| 220 | #define CFG_PROMPT "# " /* Monitor Command Prompt */ |
| 221 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 222 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 223 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 224 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 225 | |
| 226 | #define CFG_HUSH_PARSER |
| 227 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 228 | #define CONFIG_AUTO_COMPLETE |
| 229 | |
| 230 | #define CFG_MEMTEST_START PHYS_SDRAM_1 |
| 231 | #define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE |
| 232 | |
| 233 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
| 234 | |
| 235 | #define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ |
| 236 | |
| 237 | /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. |
| 238 | * This time is further subdivided by a local divisor. |
| 239 | */ |
| 240 | #define CFG_TIMERBASE OMAP1510_TIMER1_BASE |
| 241 | #define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ |
| 242 | #define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) |
| 243 | |
| 244 | #define OMAP5910_DPLL_DIV 1 |
| 245 | #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ |
| 246 | (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) |
| 247 | |
| 248 | #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ |
| 249 | #define OMAP5910_LCD_DIV 2 /* CKL/4 */ |
| 250 | #define OMAP5910_ARM_DIV 0 /* CKL/1 */ |
| 251 | #define OMAP5910_DSP_DIV 0 /* CKL/1 */ |
| 252 | #define OMAP5910_TC_DIV 1 /* CKL/2 */ |
| 253 | #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ |
| 254 | #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ |
| 255 | |
| 256 | #define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ |
| 257 | #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ |
| 258 | (OMAP5910_LCD_DIV << 2) | \ |
| 259 | (OMAP5910_ARM_DIV << 4) | \ |
| 260 | (OMAP5910_DSP_DIV << 6) | \ |
| 261 | (OMAP5910_TC_DIV << 8) | \ |
| 262 | (OMAP5910_DSP_MMU_DIV << 10) | \ |
| 263 | (OMAP5910_ARM_TIM_SEL << 12)) |
| 264 | |
| 265 | #endif /* __CONFIG_H */ |