Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Renesas Solutions ECOVEC board |
| 4 | * |
| 5 | * Copyright (C) 2009 - 2011 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> |
| 7 | * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __ECOVEC_H |
| 11 | #define __ECOVEC_H |
| 12 | |
| 13 | /* |
| 14 | * Address Interface BusWidth |
| 15 | *----------------------------------------- |
| 16 | * 0x0000_0000 U-Boot 16bit |
| 17 | * 0x0004_0000 Linux romImage 16bit |
| 18 | * 0x0014_0000 MTD for Linux 16bit |
| 19 | * 0x0400_0000 Internal I/O 16/32bit |
| 20 | * 0x0800_0000 DRAM 32bit |
| 21 | * 0x1800_0000 MFI 16bit |
| 22 | */ |
| 23 | |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 24 | #define CONFIG_CPU_SH7724 1 |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 25 | |
| 26 | #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000 |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 27 | |
Vladimir Zapolskiy | 18a40e8 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 28 | #define CONFIG_DISPLAY_BOARDINFO |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 29 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 30 | |
| 31 | /* I2C */ |
Nobuhiro Iwamatsu | 2035d77 | 2013-10-29 13:33:51 +0900 | [diff] [blame] | 32 | #define CONFIG_SYS_I2C |
| 33 | #define CONFIG_SYS_I2C_SH |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 34 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
Nobuhiro Iwamatsu | 2035d77 | 2013-10-29 13:33:51 +0900 | [diff] [blame] | 35 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 |
| 36 | #define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 |
| 37 | #define CONFIG_SYS_I2C_SH_SPEED0 100000 |
| 38 | #define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 |
| 39 | #define CONFIG_SYS_I2C_SH_SPEED1 100000 |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 40 | #define CONFIG_SH_I2C_DATA_HIGH 4 |
| 41 | #define CONFIG_SH_I2C_DATA_LOW 5 |
| 42 | #define CONFIG_SH_I2C_CLOCK 41666666 |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 43 | |
| 44 | /* Ether */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 45 | #define CONFIG_SH_ETHER_USE_PORT (0) |
| 46 | #define CONFIG_SH_ETHER_PHY_ADDR (0x1f) |
Nobuhiro Iwamatsu | e50edf9 | 2011-12-01 18:48:38 +0000 | [diff] [blame] | 47 | #define CONFIG_PHY_SMSC 1 |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 48 | #define CONFIG_BITBANGMII |
| 49 | #define CONFIG_BITBANGMII_MULTI |
Nobuhiro Iwamatsu | a80a661 | 2012-05-16 10:23:21 +0900 | [diff] [blame] | 50 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 51 | |
| 52 | /* USB / R8A66597 */ |
| 53 | #define CONFIG_USB_R8A66597_HCD |
| 54 | #define CONFIG_R8A66597_BASE_ADDR 0xA4D80000 |
| 55 | #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ |
| 56 | #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ |
| 57 | #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ |
| 58 | #define CONFIG_SUPERH_ON_CHIP_R8A66597 |
| 59 | |
| 60 | /* undef to save memory */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 61 | /* Monitor Command Prompt */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 62 | /* Buffer size for Console output */ |
| 63 | #define CONFIG_SYS_PBSIZE 256 |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 64 | /* List of legal baudrate settings for this board */ |
| 65 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
| 66 | |
| 67 | /* SCIF */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 68 | #define CONFIG_SCIF 1 |
| 69 | #define CONFIG_CONS_SCIF0 1 |
| 70 | |
| 71 | /* Suppress display of console information at boot */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 72 | |
| 73 | /* SDRAM */ |
| 74 | #define CONFIG_SYS_SDRAM_BASE (0x88000000) |
| 75 | #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) |
| 76 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
| 77 | |
| 78 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
| 79 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024) |
| 80 | /* Enable alternate, more extensive, memory test */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 81 | /* Scratch address used by the alternate memory test */ |
| 82 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
| 83 | |
| 84 | /* Enable temporary baudrate change while serial download */ |
| 85 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
| 86 | |
| 87 | /* FLASH */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 88 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
| 89 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 90 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
| 91 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
| 92 | |
| 93 | /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ |
| 94 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 95 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 96 | |
| 97 | /* Timeout for Flash erase operations (in ms) */ |
| 98 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
| 99 | /* Timeout for Flash write operations (in ms) */ |
| 100 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
| 101 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
| 102 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
| 103 | /* Timeout for Flash clear lock bit operations (in ms) */ |
| 104 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
| 105 | |
| 106 | /* |
| 107 | * Use hardware flash sectors protection instead |
| 108 | * of U-Boot software protection |
| 109 | */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 110 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
| 111 | |
| 112 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ |
| 113 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
| 114 | /* Monitor size */ |
| 115 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| 116 | /* Size of DRAM reserved for malloc() use */ |
| 117 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 118 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
| 119 | |
| 120 | /* ENV setting */ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 121 | #define CONFIG_ENV_OVERWRITE 1 |
| 122 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 123 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
| 124 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
| 125 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ |
| 126 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
| 127 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
| 128 | |
| 129 | /* Board Clock */ |
| 130 | #define CONFIG_SYS_CLK_FREQ 41666666 |
Nobuhiro Iwamatsu | 684a501 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 131 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Nobuhiro Iwamatsu | 6d1d5cf | 2011-11-15 12:29:06 +0900 | [diff] [blame] | 132 | |
| 133 | #endif /* __ECOVEC_H */ |