Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Michal Simek | f7c8e49 | 2018-03-28 15:36:36 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Configuration for Xilinx ZynqMP zcu104 |
| 4 | * |
| 5 | * (C) Copyright 2017 Xilinx, Inc. |
| 6 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | f7c8e49 | 2018-03-28 15:36:36 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_ZYNQMP_ZCU104_H |
| 10 | #define __CONFIG_ZYNQMP_ZCU104_H |
| 11 | |
| 12 | #define CONFIG_ZYNQ_SDHCI1 |
| 13 | #define CONFIG_SYS_I2C_MAX_HOPS 1 |
| 14 | #define CONFIG_SYS_NUM_I2C_BUSES 9 |
| 15 | #define CONFIG_SYS_I2C_BUSES { \ |
| 16 | {0, {I2C_NULL_HOP} }, \ |
| 17 | {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ |
| 18 | {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ |
| 19 | {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ |
| 20 | {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ |
| 21 | {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ |
| 22 | {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ |
| 23 | {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ |
| 24 | {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \ |
| 25 | } |
| 26 | |
| 27 | #define CONFIG_PCA953X |
| 28 | |
Michal Simek | f7c8e49 | 2018-03-28 15:36:36 +0200 | [diff] [blame] | 29 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 30 | |
| 31 | #include <configs/xilinx_zynqmp.h> |
| 32 | |
| 33 | #endif /* __CONFIG_ZYNQMP_ZCU104_H */ |