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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ace3be4f15875d74344336b9754c14274f940969 / . / board / dbau1x00 / lowlevel_init.S
blob: 409f8ee47701a3efe710cb190561deb13f95cf2c [file] [log] [blame]
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]1/* Memory sub-system initialization code */
2
3#include <config.h>
Daniel Schwierzeck76ada5f2015-12-21 16:35:14 +0100[diff] [blame]4#include <mach/au1x00.h>
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]5#include <asm/regdef.h>
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]6#include <asm/mipsregs.h>
7
8#define AU1500_SYS_ADDR 0xB1900000
9#define sys_endian 0x0038
10#define CP0_Config0 $16
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]11#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
12#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]13
14 .text
15 .set noreorder
16 .set mips32
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]17
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame]18 .globl lowlevel_init
19lowlevel_init:
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]20 /*
21 * Step 1) Establish CPU endian mode.
22 * Db1500-specific:
23 * Switch S1.1 Off(bit7 reads 1) is Little Endian
24 * Switch S1.1 On (bit7 reads 0) is Big Endian
25 */
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]26#ifdef CONFIG_DBAU1550
27 li t0, MEM_STCFG2
28 li t1, 0x00000040
29 sw t1, 0(t0)
30
31 li t0, MEM_STTIME2
32 li t1, 0x22080a20
33 sw t1, 0(t0)
34
35 li t0, MEM_STADDR2
36 li t1, 0x10c03f00
37 sw t1, 0(t0)
38#else
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]39 li t0, MEM_STCFG1
40 li t1, 0x00000080
41 sw t1, 0(t0)
42
43 li t0, MEM_STTIME1
44 li t1, 0x22080a20
45 sw t1, 0(t0)
46
47 li t0, MEM_STADDR1
48 li t1, 0x10c03f00
49 sw t1, 0(t0)
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]50#endif
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]51
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]52 li t0, DB1XX0_BCSR_ADDR
53 lw t1,8(t0)
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]54 andi t1,t1,0x80
55 beq zero,t1,big_endian
56 nop
57little_endian:
58
59 /* Change Au1 core to little endian */
60 li t0, AU1500_SYS_ADDR
61 li t1, 1
62 sw t1, sys_endian(t0)
63 mfc0 t2, CP0_CONFIG
64 mtc0 t2, CP0_CONFIG
65 nop
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]66 nop
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]67
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]68 /* Big Endian is default so nothing to do but fall through */
69
70big_endian:
71
72 /*
73 * Step 2) Establish Status Register
74 * (set BEV, clear ERL, clear EXL, clear IE)
75 */
76 li t1, 0x00400000
77 mtc0 t1, CP0_STATUS
78
79 /*
80 * Step 3) Establish CP0 Config0
81 * (set OD, set K0=3)
82 */
83 li t1, 0x00080003
84 mtc0 t1, CP0_CONFIG
85
86 /*
87 * Step 4) Disable Watchpoint facilities
88 */
89 li t1, 0x00000000
90 mtc0 t1, CP0_WATCHLO
91 mtc0 t1, CP0_IWATCHLO
92 /*
93 * Step 5) Disable the performance counters
94 */
95 mtc0 zero, CP0_PERFORMANCE
96 nop
97
98 /*
99 * Step 6) Establish EJTAG Debug register
100 */
101 mtc0 zero, CP0_DEBUG
102 nop
103
104 /*
105 * Step 7) Establish Cause
106 * (set IV bit)
107 */
108 li t1, 0x00800000
109 mtc0 t1, CP0_CAUSE
110
111 /* Establish Wired (and Random) */
112 mtc0 zero, CP0_WIRED
113 nop
114
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]115#ifdef CONFIG_DBAU1550
116 /* No workaround if running from ram */
117 lui t0, 0xffc0
118 lui t3, 0xbfc0
119 and t1, ra, t0
120 bne t1, t3, noCacheJump
121 nop
122
123 /*** From AMD YAMON ***/
124 /*
125 * Step 8) Initialize the caches
126 */
127 li t0, (16*1024)
128 li t1, 32
129 li t2, 0x80000000
130 addu t3, t0, t2
131cacheloop:
132 cache 0, 0(t2)
133 cache 1, 0(t2)
134 addu t2, t1
135 bne t2, t3, cacheloop
136 nop
137
138 /* Save return address */
139 move t3, ra
140
141 /* Run from cacheable space now */
142 bal cachehere
143 nop
144cachehere:
145 li t1, ~0x20000000 /* convert to KSEG0 */
146 and t0, ra, t1
147 addi t0, 5*4 /* 5 insns beyond cachehere */
148 jr t0
149 nop
150
151 /* Restore return address */
152 move ra, t3
153
154 /*
155 * Step 9) Initialize the TLB
156 */
157 li t0, 0 # index value
158 li t1, 0x00000000 # entryhi value
159 li t2, 32 # 32 entries
160
161tlbloop:
162 /* Probe TLB for matching EntryHi */
163 mtc0 t1, CP0_ENTRYHI
164 tlbp
165 nop
166
167 /* Examine Index[P], 1=no matching entry */
168 mfc0 t3, CP0_INDEX
169 li t4, 0x80000000
170 and t3, t4, t3
171 addiu t1, t1, 1 # increment t1 (asid)
172 beq zero, t3, tlbloop
173 nop
174
175 /* Initialize the TLB entry */
176 mtc0 t0, CP0_INDEX
177 mtc0 zero, CP0_ENTRYLO0
178 mtc0 zero, CP0_ENTRYLO1
179 mtc0 zero, CP0_PAGEMASK
180 tlbwi
181
182 /* Do it again */
183 addiu t0, t0, 1
184 bne t0, t2, tlbloop
185 nop
186
Heiko Schocherad882972006-04-11 14:53:29 +0200[diff] [blame]187#endif /* CONFIG_DBAU1550 */
188
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]189 /* First setup pll:s to make serial work ok */
190 /* We have a 12 MHz crystal */
191 li t0, SYS_CPUPLL
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]192 li t1, CPU_SCALE /* CPU clock */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]193 sw t1, 0(t0)
194 sync
195 nop
196 nop
197
198 /* wait 1mS for clocks to settle */
199 li t1, MEM_1MS
2001: add t1, -1
201 bne t1, zero, 1b
202 nop
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]203 /* Setup AUX PLL */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]204 li t0, SYS_AUXPLL
205 li t1, 0x20 /* 96 MHz */
206 sw t1, 0(t0) /* aux pll */
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]207 sync
208
Heiko Schocherad882972006-04-11 14:53:29 +0200[diff] [blame]209#ifdef CONFIG_DBAU1550
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]210 /* Static memory controller */
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]211 /* RCE0 - can not change while fetching, do so from icache */
212 move t2, ra /* Store return address */
213 bal getAddr
214 nop
215
216getAddr:
217 move t1, ra
218 move ra, t2 /* Move return addess back */
219
220 cache 0x14,0(t1)
221 cache 0x14,32(t1)
222 /*** /From YAMON ***/
223
224noCacheJump:
225#endif /* CONFIG_DBAU1550 */
226
227#ifdef CONFIG_DBAU1550
228 li t0, MEM_STTIME0
229 li t1, 0x040181D7
230 sw t1, 0(t0)
231
232 /* RCE0 AMD MirrorBit Flash (?) */
233 li t0, MEM_STCFG0
234 li t1, 0x00000003
235 sw t1, 0(t0)
236
237 li t0, MEM_STADDR0
238 li t1, 0x11803E00
239 sw t1, 0(t0)
240#else /* CONFIG_DBAU1550 */
241 li t0, MEM_STTIME0
Heiko Schocherad882972006-04-11 14:53:29 +0200[diff] [blame]242 li t1, 0x040181D7
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]243 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]244
245 /* RCE0 AMD 29LV640M MirrorBit Flash */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]246 li t0, MEM_STCFG0
247 li t1, 0x00000013
248 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]249
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]250 li t0, MEM_STADDR0
251 li t1, 0x11E03F80
252 sw t1, 0(t0)
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]253#endif /* CONFIG_DBAU1550 */
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]254
255 /* RCE1 CPLD Board Logic */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]256 li t0, MEM_STCFG1
257 li t1, 0x00000080
258 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]259
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]260 li t0, MEM_STTIME1
261 li t1, 0x22080a20
262 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]263
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]264 li t0, MEM_STADDR1
265 li t1, 0x10c03f00
266 sw t1, 0(t0)
267
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]268#ifdef CONFIG_DBAU1550
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]269 /* RCE2 CPLD Board Logic */
270 li t0, MEM_STCFG2
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]271 li t1, 0x00000040
272 sw t1, 0(t0)
273
274 li t0, MEM_STTIME2
275 li t1, 0x22080a20
276 sw t1, 0(t0)
277
278 li t0, MEM_STADDR2
279 li t1, 0x10c03f00
280 sw t1, 0(t0)
281#else
282 li t0, MEM_STCFG2
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]283 li t1, 0x00000000
284 sw t1, 0(t0)
285
286 li t0, MEM_STTIME2
287 li t1, 0x00000000
288 sw t1, 0(t0)
289
290 li t0, MEM_STADDR2
291 li t1, 0x00000000
292 sw t1, 0(t0)
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]293#endif
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]294
295 /* RCE3 PCMCIA 250ns */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]296 li t0, MEM_STCFG3
297 li t1, 0x00000002
298 sw t1, 0(t0)
299
300 li t0, MEM_STTIME3
301 li t1, 0x280E3E07
302 sw t1, 0(t0)
303
304 li t0, MEM_STADDR3
305 li t1, 0x10000000
306 sw t1, 0(t0)
307
308 sync
309
310 /* Set peripherals to a known state */
311 li t0, IC0_CFG0CLR
312 li t1, 0xFFFFFFFF
313 sw t1, 0(t0)
314
315 li t0, IC0_CFG0CLR
316 sw t1, 0(t0)
317
318 li t0, IC0_CFG1CLR
319 sw t1, 0(t0)
320
321 li t0, IC0_CFG2CLR
322 sw t1, 0(t0)
323
324 li t0, IC0_SRCSET
325 sw t1, 0(t0)
326
327 li t0, IC0_ASSIGNSET
328 sw t1, 0(t0)
329
330 li t0, IC0_WAKECLR
331 sw t1, 0(t0)
332
333 li t0, IC0_RISINGCLR
334 sw t1, 0(t0)
335
336 li t0, IC0_FALLINGCLR
337 sw t1, 0(t0)
338
339 li t0, IC0_TESTBIT
340 li t1, 0x00000000
341 sw t1, 0(t0)
342 sync
343
344 li t0, IC1_CFG0CLR
345 li t1, 0xFFFFFFFF
346 sw t1, 0(t0)
347
348 li t0, IC1_CFG0CLR
349 sw t1, 0(t0)
350
351 li t0, IC1_CFG1CLR
352 sw t1, 0(t0)
353
354 li t0, IC1_CFG2CLR
355 sw t1, 0(t0)
356
357 li t0, IC1_SRCSET
358 sw t1, 0(t0)
359
360 li t0, IC1_ASSIGNSET
361 sw t1, 0(t0)
362
363 li t0, IC1_WAKECLR
364 sw t1, 0(t0)
365
366 li t0, IC1_RISINGCLR
367 sw t1, 0(t0)
368
369 li t0, IC1_FALLINGCLR
370 sw t1, 0(t0)
371
372 li t0, IC1_TESTBIT
373 li t1, 0x00000000
374 sw t1, 0(t0)
375 sync
376
377 li t0, SYS_FREQCTRL0
378 li t1, 0x00000000
379 sw t1, 0(t0)
380
381 li t0, SYS_FREQCTRL1
382 li t1, 0x00000000
383 sw t1, 0(t0)
384
385 li t0, SYS_CLKSRC
386 li t1, 0x00000000
387 sw t1, 0(t0)
388
389 li t0, SYS_PININPUTEN
390 li t1, 0x00000000
391 sw t1, 0(t0)
392 sync
393
394 li t0, 0xB1100100
395 li t1, 0x00000000
396 sw t1, 0(t0)
397
398 li t0, 0xB1400100
399 li t1, 0x00000000
400 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]401
402
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]403 li t0, SYS_WAKEMSK
404 li t1, 0x00000000
405 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]406
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]407 li t0, SYS_WAKESRC
408 li t1, 0x00000000
409 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]410
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]411 /* wait 1mS before setup */
412 li t1, MEM_1MS
4131: add t1, -1
414 bne t1, zero, 1b
415 nop
416
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]417#ifdef CONFIG_DBAU1550
418/* SDCS 0,1,2 DDR SDRAM */
419 li t0, MEM_SDMODE0
420 li t1, 0x04276221
421 sw t1, 0(t0)
422
423 li t0, MEM_SDMODE1
424 li t1, 0x04276221
425 sw t1, 0(t0)
426
427 li t0, MEM_SDMODE2
428 li t1, 0x04276221
429 sw t1, 0(t0)
430
431 li t0, MEM_SDADDR0
432 li t1, 0xe21003f0
433 sw t1, 0(t0)
434
435 li t0, MEM_SDADDR1
436 li t1, 0xe21043f0
437 sw t1, 0(t0)
438
439 li t0, MEM_SDADDR2
440 li t1, 0xe21083f0
441 sw t1, 0(t0)
442
443 sync
444
445 li t0, MEM_SDCONFIGA
446 li t1, 0x9030060a /* Program refresh - disabled */
447 sw t1, 0(t0)
448 sync
449
450 li t0, MEM_SDCONFIGB
451 li t1, 0x00028000
452 sw t1, 0(t0)
453 sync
454
455 li t0, MEM_SDPRECMD /* Precharge all */
456 li t1, 0
457 sw t1, 0(t0)
458 sync
459
460 li t0, MEM_SDWRMD0
461 li t1, 0x40000000
462 sw t1, 0(t0)
463 sync
464
465 li t0, MEM_SDWRMD1
466 li t1, 0x40000000
467 sw t1, 0(t0)
468 sync
469
470 li t0, MEM_SDWRMD2
471 li t1, 0x40000000
472 sw t1, 0(t0)
473 sync
474
475 li t0, MEM_SDWRMD0
476 li t1, 0x00000063
477 sw t1, 0(t0)
478 sync
479
480 li t0, MEM_SDWRMD1
481 li t1, 0x00000063
482 sw t1, 0(t0)
483 sync
484
485 li t0, MEM_SDWRMD2
486 li t1, 0x00000063
487 sw t1, 0(t0)
488 sync
489
490 li t0, MEM_SDPRECMD /* Precharge all */
491 sw zero, 0(t0)
492 sync
493
494 /* Issue 2 autoref */
495 li t0, MEM_SDAUTOREF
496 sw zero, 0(t0)
497 sync
498
499 li t0, MEM_SDAUTOREF
500 sw zero, 0(t0)
501 sync
502
503 /* Enable refresh */
504 li t0, MEM_SDCONFIGA
505 li t1, 0x9830060a /* Program refresh - enabled */
506 sw t1, 0(t0)
507 sync
508
509#else /* CONFIG_DBAU1550 */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]510/* SDCS 0,1 SDRAM */
511 li t0, MEM_SDMODE0
512 li t1, 0x005522AA
513 sw t1, 0(t0)
514
515 li t0, MEM_SDMODE1
516 li t1, 0x005522AA
517 sw t1, 0(t0)
518
519 li t0, MEM_SDMODE2
520 li t1, 0x00000000
521 sw t1, 0(t0)
522
523 li t0, MEM_SDADDR0
524 li t1, 0x001003F8
525 sw t1, 0(t0)
526
527
528 li t0, MEM_SDADDR1
529 li t1, 0x001023F8
530 sw t1, 0(t0)
531
532 li t0, MEM_SDADDR2
533 li t1, 0x00000000
534 sw t1, 0(t0)
535
536 sync
537
538 li t0, MEM_SDREFCFG
539 li t1, 0x64000C24 /* Disable */
540 sw t1, 0(t0)
541 sync
542
543 li t0, MEM_SDPRECMD
544 sw zero, 0(t0)
545 sync
546
547 li t0, MEM_SDAUTOREF
548 sw zero, 0(t0)
549 sync
550 sw zero, 0(t0)
551 sync
552
553 li t0, MEM_SDREFCFG
554 li t1, 0x66000C24 /* Enable */
555 sw t1, 0(t0)
556 sync
557
558 li t0, MEM_SDWRMD0
559 li t1, 0x00000033
560 sw t1, 0(t0)
561 sync
562
563 li t0, MEM_SDWRMD1
564 li t1, 0x00000033
565 sw t1, 0(t0)
566 sync
567
wdenkff36fd82005-01-09 22:28:56 +0000[diff] [blame]568#endif /* CONFIG_DBAU1550 */
wdenk63f34912004-01-02 15:01:32 +0000[diff] [blame]569 /* wait 1mS after setup */
570 li t1, MEM_1MS
5711: add t1, -1
572 bne t1, zero, 1b
573 nop
574
575 li t0, SYS_PINFUNC
576 li t1, 0x00008080
577 sw t1, 0(t0)
578
579 li t0, SYS_TRIOUTCLR
580 li t1, 0x00001FFF
581 sw t1, 0(t0)
582
583 li t0, SYS_OUTPUTCLR
584 li t1, 0x00008000
585 sw t1, 0(t0)
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]586 sync
587
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]588 jr ra
wdenk5da627a2003-10-09 20:09:04 +0000[diff] [blame]589 nop