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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop8e429b32008-05-08 18:52:23 +02002/*
3 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Pop8e429b32008-05-08 18:52:23 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9263EK board.
Stelian Pop8e429b32008-05-08 18:52:23 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Xu, Hongcd46b0f2011-06-10 21:31:26 +000013/*
14 * SoC must be defined first, before hardware.h is included.
15 * In this case SoC is defined in boards.cfg.
16 */
17#include <asm/hardware.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020018
Xu, Hongcd46b0f2011-06-10 21:31:26 +000019/* ARM asynchronous clock */
20#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Xu, Hongcd46b0f2011-06-10 21:31:26 +000022
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020023#define CONFIG_ARCH_CPU_INIT
Stelian Pop8e429b32008-05-08 18:52:23 +020024
25#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
26#define CONFIG_SETUP_MEMORY_TAGS 1
27#define CONFIG_INITRD_TAG 1
28
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020029#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +020030#define CONFIG_SKIP_LOWLEVEL_INIT
Xu, Hongcd46b0f2011-06-10 21:31:26 +000031#else
32#define CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020033#endif
Stelian Pop8e429b32008-05-08 18:52:23 +020034
35/*
36 * Hardware drivers
37 */
Xu, Hongcd46b0f2011-06-10 21:31:26 +000038#define CONFIG_ATMEL_LEGACY
Stelian Pop8e429b32008-05-08 18:52:23 +020039
Stelian Pop56a24792008-05-08 14:52:31 +020040/* LCD */
Stelian Pop56a24792008-05-08 14:52:31 +020041#define LCD_BPP LCD_COLOR8
42#define CONFIG_LCD_LOGO 1
43#undef LCD_TEST_PATTERN
44#define CONFIG_LCD_INFO 1
45#define CONFIG_LCD_INFO_BELOW_LOGO 1
Stelian Pop56a24792008-05-08 14:52:31 +020046#define CONFIG_ATMEL_LCD 1
47#define CONFIG_ATMEL_LCD_BGR555 1
Stelian Pop56a24792008-05-08 14:52:31 +020048
Stelian Pop8e429b32008-05-08 18:52:23 +020049/*
50 * BOOTP options
51 */
52#define CONFIG_BOOTP_BOOTFILESIZE 1
Stelian Pop8e429b32008-05-08 18:52:23 +020053
Stelian Pop8e429b32008-05-08 18:52:23 +020054/* SDRAM */
Xu, Hongcd46b0f2011-06-10 21:31:26 +000055#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
56#define CONFIG_SYS_SDRAM_SIZE 0x04000000
57
58#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang0b8908f2017-04-18 15:31:00 +080059 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Pop8e429b32008-05-08 18:52:23 +020060
Stelian Pop8e429b32008-05-08 18:52:23 +020061/* NOR flash, if populated */
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020062#ifdef CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020064#define CONFIG_FLASH_CFI_DRIVER 1
65#define PHYS_FLASH_1 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
67#define CONFIG_SYS_MAX_FLASH_SECT 256
68#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020069
70#define CONFIG_SYS_MONITOR_SEC 1:0-3
71#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
72#define CONFIG_SYS_MONITOR_LEN (256 << 10)
esw@bus-elektronik.de5e7d0912012-03-19 05:18:17 +000073#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020074#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
75
76/* Address and size of Primary Environment Sector */
esw@bus-elektronik.de5e7d0912012-03-19 05:18:17 +000077#define CONFIG_ENV_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020078
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020079#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut93ea89f2012-09-23 17:41:23 +020080 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020081 "update=" \
82 "protect off ${monitor_base} +${filesize};" \
83 "erase ${monitor_base} +${filesize};" \
Andreas Bießmann88461f12012-06-28 02:32:32 +000084 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020085 "protect on ${monitor_base} +${filesize}\0"
86
87#ifndef CONFIG_SKIP_LOWLEVEL_INIT
88#define MASTER_PLL_MUL 171
89#define MASTER_PLL_DIV 14
Jens Scharsig1b34f002010-02-03 22:47:18 +010090#define MASTER_PLL_OUT 3
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020091
92/* clocks */
93#define CONFIG_SYS_MOR_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +010094 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
95#define CONFIG_SYS_PLLAR_VAL \
96 (AT91_PMC_PLLAR_29 | \
97 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
98 AT91_PMC_PLLXR_PLLCOUNT(63) | \
99 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
100 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200101
102/* PCK/2 = MCK Master Clock from PLLA */
103#define CONFIG_SYS_MCKR1_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100104 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
105 AT91_PMC_MCKR_MDIV_2)
106
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200107/* PCK/2 = MCK Master Clock from PLLA */
108#define CONFIG_SYS_MCKR2_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100109 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
110 AT91_PMC_MCKR_MDIV_2)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200111
112/* define PDC[31:16] as DATA[31:16] */
113#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
114/* no pull-up for D[31:16] */
115#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
116/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100117#define CONFIG_SYS_MATRIX_EBICSA_VAL \
118 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
119 AT91_MATRIX_CSA_EBI_CS1A)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200120
121/* SDRAM */
122/* SDRAMC_MR Mode register */
123#define CONFIG_SYS_SDRC_MR_VAL1 0
124/* SDRAMC_TR - Refresh Timer register */
125#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
126/* SDRAMC_CR - Configuration register*/
127#define CONFIG_SYS_SDRC_CR_VAL \
128 (AT91_SDRAMC_NC_9 | \
129 AT91_SDRAMC_NR_13 | \
130 AT91_SDRAMC_NB_4 | \
131 AT91_SDRAMC_CAS_3 | \
132 AT91_SDRAMC_DBW_32 | \
133 (1 << 8) | /* Write Recovery Delay */ \
134 (7 << 12) | /* Row Cycle Delay */ \
135 (2 << 16) | /* Row Precharge Delay */ \
136 (2 << 20) | /* Row to Column Delay */ \
137 (5 << 24) | /* Active to Precharge Delay */ \
138 (1 << 28)) /* Exit Self Refresh to Active Delay */
139
140/* Memory Device Register -> SDRAM */
141#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
142#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
143#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
144#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
145#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
146#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
147#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
148#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
149#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
150#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
151#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
152#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
153#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
154#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
155#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
156#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
157#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
158#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
159
160/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100161#define CONFIG_SYS_SMC0_SETUP0_VAL \
162 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
163 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
164#define CONFIG_SYS_SMC0_PULSE0_VAL \
165 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
166 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200167#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100168 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200169#define CONFIG_SYS_SMC0_MODE0_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100170 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
171 AT91_SMC_MODE_DBW_16 | \
172 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200173
174/* user reset enable */
175#define CONFIG_SYS_RSTC_RMR_VAL \
176 (AT91_RSTC_KEY | \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100177 AT91_RSTC_MR_URSTEN | \
178 AT91_RSTC_MR_ERSTL(15))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200179
180/* Disable Watchdog */
181#define CONFIG_SYS_WDTC_WDMR_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100182 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
183 AT91_WDT_MR_WDV(0xfff) | \
184 AT91_WDT_MR_WDDIS | \
185 AT91_WDT_MR_WDD(0xfff))
186
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200187#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200188#endif
189
190/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100191#ifdef CONFIG_CMD_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000193#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100195/* our ALE is AD21 */
196#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
197/* our CLE is AD22 */
198#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000199#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
200#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100201#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200202
203/* Ethernet */
Stelian Pop8e429b32008-05-08 18:52:23 +0200204#define CONFIG_RESET_PHY_R 1
Heiko Schocher4535a242013-11-18 08:07:23 +0100205#define CONFIG_AT91_WANTS_COMMON_PHY
Stelian Pop8e429b32008-05-08 18:52:23 +0200206
207/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +0100208#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800209#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Stelian Pop8e429b32008-05-08 18:52:23 +0200210#define CONFIG_USB_OHCI_NEW 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
212#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
213#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
214#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop8e429b32008-05-08 18:52:23 +0200215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop8e429b32008-05-08 18:52:23 +0200217
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000218#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop8e429b32008-05-08 18:52:23 +0200220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200222
223/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wenyou.Yang@microchip.comeab36f62017-07-21 13:40:09 +0800224#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200225#define CONFIG_ENV_SIZE 0x4200
Wenyou.Yang@microchip.comeab36f62017-07-21 13:40:09 +0800226#define CONFIG_ENV_SECT_SIZE 0x210
227#define CONFIG_ENV_SPI_MAX_HZ 15000000
228#define CONFIG_BOOTCOMMAND "sf probe 0; " \
229 "sf read 0x22000000 0x84000 0x294000; " \
230 "bootm 0x22000000"
Stelian Pop8e429b32008-05-08 18:52:23 +0200231
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200232#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200233
234/* bootstrap + u-boot + env + linux in nandflash */
Nicolas Ferre7b8b19f2018-05-09 10:30:25 +0300235#define CONFIG_ENV_OFFSET 0x140000
Bo Shen0c58cfa2013-02-20 00:16:25 +0000236#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200237#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Bo Shen0c58cfa2013-02-20 00:16:25 +0000238#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
Stelian Pop8e429b32008-05-08 18:52:23 +0200239#endif
240
Stelian Pop8e429b32008-05-08 18:52:23 +0200241/*
242 * Size of malloc() pool
243 */
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000244#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop8e429b32008-05-08 18:52:23 +0200245
Stelian Pop8e429b32008-05-08 18:52:23 +0200246#endif