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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekdea4d2f2017-11-02 10:54:48 +01002/*
3 * (C) Copyright 2013 - 2017 Xilinx.
4 *
5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
Michal Simekdea4d2f2017-11-02 10:54:48 +01007 */
8
9#ifndef __CONFIG_ZYNQ_CSE_H
10#define __CONFIG_ZYNQ_CSE_H
11
12#define CONFIG_SKIP_LOWLEVEL_INIT
13#define CONFIG_SYS_DCACHE_OFF
14#define CONFIG_SYS_ICACHE_OFF
15
16#include <configs/zynq-common.h>
17
18/* Undef unneeded configs */
19#undef CONFIG_EXTRA_ENV_SETTINGS
20#undef CONFIG_BOARD_LATE_INIT
Michal Simekdea4d2f2017-11-02 10:54:48 +010021#undef CONFIG_ZLIB
22#undef CONFIG_GZIP
23
Michal Simekdea4d2f2017-11-02 10:54:48 +010024#undef CONFIG_SYS_CBSIZE
25#undef CONFIG_BOOTM_VXWORKS
26#undef CONFIG_BOOTM_LINUX
27
28#define CONFIG_SYS_CBSIZE 1024
29
Michal Simekdea4d2f2017-11-02 10:54:48 +010030#undef CONFIG_SYS_INIT_RAM_ADDR
31#undef CONFIG_SYS_INIT_RAM_SIZE
32#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
33#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
34#undef CONFIG_SPL_BSS_START_ADDR
35#undef CONFIG_SPL_BSS_MAX_SIZE
36#define CONFIG_SPL_BSS_START_ADDR 0x20000
37#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
38
Michal Simekdea4d2f2017-11-02 10:54:48 +010039#endif /* __CONFIG_ZYNQ_CSE_H */