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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_ETX094 1 /* ...on a ETX_094 board */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 57600
43#if 0
44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
45#else
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47#endif
48
49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
50
51#define CONFIG_BOARD_TYPES 1 /* support board types */
52
53#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */
54#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
55#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */
56
57#define CONFIG_ETHADDR 08:00:06:00:00:00
58
59#ifdef CONFIG_ETHADDR
60#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */
61#endif
62
63#undef CONFIG_BOOTARGS
64#define CONFIG_RAMBOOTCOMMAND \
65 "bootp; " \
66 "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
67 "U-Boot_version=U-Boot-1.0.x-Date " \
68 "panic=1 " \
69 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
70 "bootm"
71#define CONFIG_NFSBOOTCOMMAND \
72 "bootp; " \
73 "setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath) " \
74 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
75 "bootm"
76#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
77
78#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
80
81#define CONFIG_WATCHDOG 1 /* watchdog enabled */
82
83#define CONFIG_STATUS_LED 1 /* Status LED enabled */
84
85#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
86
87/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88#include <cmd_confdefs.h>
89
90/*
91 * Miscellaneous configurable options
92 */
93#define CFG_LONGHELP /* undef to save memory */
94#define CFG_PROMPT "=> " /* Monitor Command Prompt */
95#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
96#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
97#else
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#endif
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103
104#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
105#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
106
107#define CFG_LOAD_ADDR 0x100000 /* default load address */
108
109#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
110
111#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
112
113/*
114 * Low Level Configuration Settings
115 * (address mappings, register initial values, etc.)
116 * You should know what you are doing if you make changes here.
117 */
118/*-----------------------------------------------------------------------
119 * Internal Memory Mapped Register
120 */
121#define CFG_IMMR 0xFFF00000
122
123/*-----------------------------------------------------------------------
124 * Definitions for initial stack pointer and data area (in DPRAM)
125 */
126#define CFG_INIT_RAM_ADDR CFG_IMMR
127#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
128#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
129#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
130#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
131
132/*-----------------------------------------------------------------------
133 * Start addresses for the final memory configuration
134 * (Set up by the startup code)
135 * Please note that CFG_SDRAM_BASE _must_ start at 0
136 */
137#define CFG_SDRAM_BASE 0x00000000
138#define CFG_FLASH_BASE 0x40000000
139#ifdef DEBUG
140#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
141#else
142#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
143#endif
144#define CFG_MONITOR_BASE CFG_FLASH_BASE
145#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
146
147/*
148 * For booting Linux, the board info and command line data
149 * have to be in the first 8 MB of memory, since this is
150 * the maximum mapped by the Linux kernel during initialization.
151 */
152#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
153/*-----------------------------------------------------------------------
154 * FLASH organization
155 */
156#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
157#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
158
159#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
160#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
161
162#define CFG_ENV_IS_IN_FLASH 1
163#ifdef CONFIG_FLASH_16BIT
164#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
165#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
166#else
167#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
168#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
169#endif
170
171/*-----------------------------------------------------------------------
172 * Hardware Information Block
173 */
174#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
175#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
176#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
177
178/*-----------------------------------------------------------------------
179 * Cache Configuration
180 */
181#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
182#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
183#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
184#endif
185
186/*-----------------------------------------------------------------------
187 * SYPCR - System Protection Control 11-9
188 * SYPCR can only be written once after reset!
189 *-----------------------------------------------------------------------
190 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
191 */
192#if defined(CONFIG_WATCHDOG)
193#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
194 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
195#else
196#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
197#endif /* CONFIG_WATCHDOG */
198
199/*-----------------------------------------------------------------------
200 * SIUMCR - SIU Module Configuration 11-6
201 *-----------------------------------------------------------------------
202 * PCMCIA config., multi-function pin tri-state
203 */
204#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
205
206/*-----------------------------------------------------------------------
207 * TBSCR - Time Base Status and Control 11-26
208 *-----------------------------------------------------------------------
209 * Clear Reference Interrupt Status, Timebase freezing enabled
210 */
211#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
212
213/*-----------------------------------------------------------------------
214 * RTCSC - Real-Time Clock Status and Control Register 11-27
215 *-----------------------------------------------------------------------
216 */
217#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
218
219/*-----------------------------------------------------------------------
220 * PISCR - Periodic Interrupt Status and Control 11-31
221 *-----------------------------------------------------------------------
222 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
223 */
224#define CFG_PISCR (PISCR_PS | PISCR_PITF)
225
226/*-----------------------------------------------------------------------
227 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
228 *-----------------------------------------------------------------------
229 * Reset PLL lock status sticky bit, timer expired status bit and timer
230 * interrupt status bit - leave PLL multiplication factor unchanged !
231 */
232#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
233
234/*-----------------------------------------------------------------------
235 * SCCR - System Clock and reset Control Register 15-27
236 *-----------------------------------------------------------------------
237 * Set clock output, timebase and RTC source and divider,
238 * power management and some other internal clocks
239 */
240#define SCCR_MASK SCCR_EBDF11
241#define CFG_SCCR (SCCR_TBS | \
242 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
243 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
244 SCCR_DFALCD00)
245
246/*-----------------------------------------------------------------------
247 * PCMCIA stuff
248 *-----------------------------------------------------------------------
249 *
250 */
251#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
252#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
253#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
254#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
255#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
256#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
257#define CFG_PCMCIA_IO_ADDR (0xEC000000)
258#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
259
260/*-----------------------------------------------------------------------
261 *
262 *-----------------------------------------------------------------------
263 *
264 */
wdenke2211742002-11-02 23:30:20 +0000265#define CFG_DER 0
266
267/*
268 * Init Memory Controller:
269 *
270 * BR0/1 and OR0/1 (FLASH)
271 */
272
273#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
274#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
275
276/* used to re-map FLASH both when starting from SRAM or FLASH:
277 * restrict access enough to keep SRAM working (if any)
278 * but not too much to meddle with FLASH accesses
279 */
280#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
281#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
282
283/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */
284#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \
wdenk8bde7f72003-06-27 21:31:46 +0000285 OR_SCY_2_CLK | OR_TRLX )
wdenke2211742002-11-02 23:30:20 +0000286
287#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
288#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
289
290#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */
291#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
292#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
293#else /* 32 bit data port */
294#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
295#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
296#endif /* CONFIG_FLASH_16BIT */
297
298#define CFG_OR1_REMAP CFG_OR0_REMAP
299#define CFG_OR1_PRELIM CFG_OR0_PRELIM
300
301/*
302 * BR2/3 and OR2/3 (SDRAM)
303 *
304 */
305#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
306#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
307#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
308
309/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
310#define CFG_OR_TIMING_SDRAM 0x00000A00
311
312#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
313#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
314
315#define CFG_OR3_PRELIM CFG_OR2_PRELIM
316#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
317
318/*
319 * Memory Periodic Timer Prescaler
320 */
321
322/* periodic timer for refresh */
323#define CFG_MAMR_PTA 23 /* start with divider for 100 MHz */
324
325/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
326#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
327#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
328
329/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
330#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
331#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
332
333/*
334 * MAMR settings for SDRAM
335 */
336
337/* 8 column SDRAM */
338#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
339 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
340 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
341/* 9 column SDRAM */
342#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
343 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
344 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
345
346
347/*
348 * Internal Definitions
349 *
350 * Boot Flags
351 */
352#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
353#define BOOTFLAG_WARM 0x02 /* Software reboot */
354
355#endif /* __CONFIG_H */