blob: 4a9093c469f6fa6050cec47c41e13af47ad53de6 [file] [log] [blame]
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -04001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for IP04 board (having BF532 processor)
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -04003 *
4 * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
5 *
6 * Copyright (c) 2005-2010 Analog Devices Inc.
7 *
8 * (C) Copyright 2000-2004
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#ifndef __CONFIG_IP04_H__
15#define __CONFIG_IP04_H__
16
17#include <asm/config-pre.h>
18
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040019/*
20 * Processor Settings
21 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050022#define CONFIG_BFIN_CPU bf532-0.5
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040023#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
24
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040025/*
26 * Clock Settings
27 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
28 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
29 */
30/* CONFIG_CLKIN_HZ is any value in Hz */
31#define CONFIG_CLKIN_HZ 10000000
32/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
33/* 1 = CLKIN / 2 */
34#define CONFIG_CLKIN_HALF 0
35/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
36/* 1 = bypass PLL */
37#define CONFIG_PLL_BYPASS 0
38/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
39/* Values can range from 0-63 (where 0 means 64) */
40#define CONFIG_VCO_MULT 40
41/* CCLK_DIV controls the core clock divider */
42/* Values can be 1, 2, 4, or 8 ONLY */
43#define CONFIG_CCLK_DIV 1
44/* SCLK_DIV controls the system clock divider */
45/* Values can range from 1-15 */
46#define CONFIG_SCLK_DIV 3
47
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040048/*
49 * Memory Settings
50 */
51#define CONFIG_MEM_ADD_WDTH 10
52#define CONFIG_MEM_SIZE 64
53
54#define CONFIG_EBIU_SDRRC_VAL 0x408
55#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
56
57#define CONFIG_EBIU_AMGCTL_VAL 0xFF
58#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
59#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
60
Sonic Zhang5dea3a72015-01-16 12:46:51 +080061#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040062#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
63
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040064/*
65 * Network Settings
66 */
67#define ADI_CMDS_NETWORK 1
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040068#define CONFIG_HOSTNAME IP04
69
70#define CONFIG_DRIVER_DM9000 1
71#define CONFIG_DM9000_NO_SROM
72#define CONFIG_DM9000_BASE 0x20100000
73#define DM9000_IO CONFIG_DM9000_BASE
74#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
75
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040076/*
77 * Flash Settings
78 */
79#define CONFIG_ENV_OVERWRITE 1
80#define CONFIG_SYS_NO_FLASH /* we have only NAND */
81
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040082/*
83 * SPI Settings
84 */
85#define CONFIG_BFIN_SPI
86#define CONFIG_ENV_SPI_MAX_HZ 30000000
87#define CONFIG_SF_DEFAULT_SPEED 30000000
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040088
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040089/*
90 * Env Storage Settings
91 */
92#define CONFIG_ENV_IS_IN_SPI_FLASH
93#define CONFIG_PREBOOT "echo starting from spi flash"
94#define CONFIG_ENV_OFFSET 0x30000
95#define CONFIG_ENV_SIZE 0x10000
96#define CONFIG_ENV_SECT_SIZE 0x10000
97
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040098/*
99 * NAND Settings
100 */
101#define CONFIG_NAND_PLAT
102#define CONFIG_SYS_NAND_BASE 0x20000000
103#define CONFIG_SYS_MAX_NAND_DEVICE 1
104
105#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
106#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400107#define BFIN_NAND_WRITE(addr, cmd) \
108 do { \
109 bfin_write8(addr, cmd); \
110 SSYNC(); \
111 } while (0)
112
113#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
114#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400115#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400116
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400117/*
118 * Misc Settings
119 */
120#define CONFIG_BAUDRATE 115200
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400121#define CONFIG_UART_CONSOLE 0
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400122
123#undef CONFIG_SHOW_BOOT_PROGRESS
124/* Enable this if bootretry required; currently it's disabled */
125#define CONFIG_BOOT_RETRY_TIME -1
126#define CONFIG_BOOTCOMMAND "run nandboot"
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400127
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400128/*
129 * Pull in common ADI header for remaining command/environment setup
130 */
131#include <configs/bfin_adi_common.h>
132
133#endif