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Shengzhou Liud3de8232012-05-03 16:51:10 +00001Overview
2=========
3The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
4
5The P1010 is a cost-effective, low-power, highly integrated host processor
6based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
7that addresses the requirements of several routing, gateways, storage, consumer,
8and industrial applications. Applications of interest include the main CPUs and
9I/O processors in network attached storage (NAS), the voice over IP (VoIP)
10router/gateway, and wireless LAN (WLAN) and industrial controllers.
11
12The P1010RDB board features are as follows:
13Memory subsystem:
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
21Interfaces:
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
24 - Lane1: x1 PCIe standard slot
25 - SATA:
26 - 1 internal SATA connector to 2.5” 160G SATA2 HDD
27 - 1 eSATA connector to rear panel
28 - 10/100/1000 BaseT Ethernet ports:
29 - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
30 - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
31 - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
32 - USB 2.0 port:
33 - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
34 - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
35 - FlexCAN ports:
36 - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
37 interface;
38 - DUART interface:
39 - DUART interface: supports two UARTs up to 115200 bps for
40 console display
41 - RJ45 connectors are used for these 2 UART ports.
42 - TDM
43 - 2 FXS ports connected via an external SLIC to the TDM interface.
44 SLIC is controllled via SPI.
45 - 1 FXO port connected via a relay to FXS for switchover to POTS
46Board connectors:
47 - Mini-ITX power supply connector
48 - JTAG/COP for debugging
49IEEE Std. 1588 signals for test and measurement
50Real-time clock on I2C bus
51POR
52 - support critical POR setting changed via switch on board
53PCB
54 - 6-layer routing (4-layer signals, 2-layer power and ground)
55
56
57Physical Memory Map on P1010RDB
58===============================
59Address Start Address End Memory type Attributes
600x0000_0000 0x3fff_ffff DDR 1G Cacheable
610xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
620xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
630xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
640xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
650xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
660xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
670xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
68
69
70Serial Port Configuration on P1010RDB
71=====================================
72Configure the serial port of the attached computer with the following values:
73 -Data rate: 115200 bps
74 -Number of data bits: 8
75 -Parity: None
76 -Number of Stop bits: 1
77 -Flow Control: Hardware/None
78
79
80Settings of DIP-switch
81======================
82 SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
83 SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
84 SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
85Note: 1 stands for 'on', 0 stands for 'off'
86
87
88Setting of hwconfig
89===================
90If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
91"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
92setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
93By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
94is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
95instead of to CAN/UART1.
96
97
98Build and burn u-boot to NOR flash
99==================================
1001. Build u-boot.bin image
101 export ARCH=powerpc
102 export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
103 make P1010RDB_NOR
104
1052. Burn u-boot.bin into NOR flash
106 => tftp $loadaddr $uboot
107 => protect off eff80000 +$filesize
108 => erase eff80000 +$filesize
109 => cp.b $loadaddr eff80000 $filesize
110
1113. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
112
113
114Alternate NOR bank
115==================
1161. Burn u-boot.bin into alternate NOR bank
117 => tftp $loadaddr $uboot
118 => protect off eef80000 +$filesize
119 => erase eef80000 +$filesize
120 => cp.b $loadaddr eef80000 $filesize
121
1222. Switch to alternate NOR bank
123 => mw.b ffb00009 1
124 => reset
125 or set SW1[8]= ON
126
127SW1[8]= OFF: Upper bank used for booting start
128SW1[8]= ON: Lower bank used for booting start
129CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
1300 - boot from upper 4 sectors
1311 - boot from lower 4 sectors
132
133
134Build and burn u-boot to NAND flash
135===================================
1361. Build u-boot.bin image
137 export ARCH=powerpc
138 export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
139 make P1010RDB_NAND
140
1412. Burn u-boot-nand.bin into NAND flash
142 => tftp $loadaddr $uboot-nand
143 => nand erase 0 $filesize
144 => nand write $loadaddr 0 $filesize
145
1463. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
147
148
Shengzhou Liud3de8232012-05-03 16:51:10 +0000149Build and burn u-boot to SPI flash
150==================================
1511. Build u-boot-spi.bin image
152 make P1010RDB_SPIFLASH_config; make
153 Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
154 Download u-boot.bin to linux and you can find some config files
155 under /usr/share such as config_xx.dat. Do below command:
156 boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
157 u-boot-spi.bin
158 to generate u-boot-spi.bin.
159
1602. Burn u-boot-spi.bin into SPI flash
161 => tftp $loadaddr $uboot-spi
162 => sf erase 0 100000
163 => sf write $loadaddr 0 $filesize
164
1653. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
166
167
Shengzhou Liud3de8232012-05-03 16:51:10 +0000168CPLD POR setting registers
169==========================
1701. Set POR switch selection register (addr 0xFFB00011) to 0.
1712. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
172 proper values.
173 If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
174 switch command by I2C.
1753. Send reset command.
176 After reset, the new POR setting will be implemented.
177
178Two examples are given in below:
179Switch from NOR to NAND boot with default frequency:
180 => i2c dev 0
181 => i2c mw 18 1 f9
182 => i2c mw 18 3 f0
183 => mw.b ffb00011 0
184 => mw.b ffb00017 1
185 => reset
186Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
187 => i2c dev 0
188 => i2c mw 18 1 f1
189 => i2c mw 18 3 f0
190 => mw.b ffb00011 0
191 => mw.b ffb00014 2
192 => mw.b ffb00015 5
193 => mw.b ffb00016 3
194 => mw.b ffb00017 f
195 => reset
196
197
Shengzhou Liud3de8232012-05-03 16:51:10 +0000198Boot Linux from network using TFTP on P1010RDB
199==============================================
200Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
201 => tftp 1000000 uImage
202 => tftp 2000000 p1010rdb.dtb
203 => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
204 => bootm 1000000 3000000 2000000
205
206
207Please contact your local field applications engineer or sales representative
208to obtain related documents, such as P1010-RDB User Guide for details.