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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
Kumar Gala7c0d4a72008-09-22 14:11:11 -050028#include <asm/cache.h>
Kumar Gala129ba612008-08-12 11:13:08 -050029#include <asm/immap_85xx.h>
30#include <asm/immap_fsl_pci.h>
31#include <asm/fsl_ddr_sdram.h>
32#include <asm/io.h>
33#include <miiphy.h>
34#include <libfdt.h>
35#include <fdt_support.h>
Liu Yu7e183ca2008-10-10 11:40:59 +080036#include <tsec.h>
Kumar Gala129ba612008-08-12 11:13:08 -050037
38#include "../common/pixis.h"
Liu Yu7e183ca2008-10-10 11:40:59 +080039#include "../common/sgmii_riser.h"
Kumar Gala129ba612008-08-12 11:13:08 -050040
Kumar Gala129ba612008-08-12 11:13:08 -050041long int fixed_sdram(void);
42
43int checkboard (void)
44{
45 printf ("Board: MPC8572DS, System ID: 0x%02x, "
46 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
47 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
48 in8(PIXIS_BASE + PIXIS_PVER));
49 return 0;
50}
51
52phys_size_t initdram(int board_type)
53{
54 phys_size_t dram_size = 0;
55
56 puts("Initializing....");
57
58#ifdef CONFIG_SPD_EEPROM
59 dram_size = fsl_ddr_sdram();
Kumar Gala129ba612008-08-12 11:13:08 -050060#else
61 dram_size = fixed_sdram();
62#endif
Dave Liue57f0fa2008-10-28 17:53:45 +080063 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
64 dram_size *= 0x100000;
Kumar Gala129ba612008-08-12 11:13:08 -050065
Kumar Gala129ba612008-08-12 11:13:08 -050066 puts(" DDR: ");
67 return dram_size;
68}
69
70#if !defined(CONFIG_SPD_EEPROM)
71/*
72 * Fixed sdram init -- doesn't use serial presence detect.
73 */
74
75phys_size_t fixed_sdram (void)
76{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Kumar Gala129ba612008-08-12 11:13:08 -050078 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
79 uint d_init;
80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
82 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
Kumar Gala129ba612008-08-12 11:13:08 -050083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
85 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
86 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
87 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
88 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
89 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
90 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
91 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
92 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
93 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Kumar Gala129ba612008-08-12 11:13:08 -050094
95#if defined (CONFIG_DDR_ECC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
97 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
98 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
Kumar Gala129ba612008-08-12 11:13:08 -050099#endif
100 asm("sync;isync");
101
102 udelay(500);
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Kumar Gala129ba612008-08-12 11:13:08 -0500105
106#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
107 d_init = 1;
108 debug("DDR - 1st controller: memory initializing\n");
109 /*
110 * Poll until memory is initialized.
111 * 512 Meg at 400 might hit this 200 times or so.
112 */
113 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
114 udelay(1000);
115 }
116 debug("DDR: memory initialized\n\n");
117 asm("sync; isync");
118 udelay(500);
119#endif
120
121 return 512 * 1024 * 1024;
122}
123
124#endif
125
126#ifdef CONFIG_PCIE1
127static struct pci_controller pcie1_hose;
128#endif
129
130#ifdef CONFIG_PCIE2
131static struct pci_controller pcie2_hose;
132#endif
133
134#ifdef CONFIG_PCIE3
135static struct pci_controller pcie3_hose;
136#endif
137
Kumar Gala2dba0de2008-10-21 08:28:33 -0500138extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
139extern void fsl_pci_init(struct pci_controller *hose);
140
Kumar Gala129ba612008-08-12 11:13:08 -0500141int first_free_busno=0;
142#ifdef CONFIG_PCI
143void pci_init_board(void)
144{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala129ba612008-08-12 11:13:08 -0500146 uint devdisr = gur->devdisr;
147 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
148 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
149
150 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
151 devdisr, io_sel, host_agent);
152
153 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
154 printf (" eTSEC1 is in sgmii mode.\n");
155 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
156 printf (" eTSEC2 is in sgmii mode.\n");
157 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
158 printf (" eTSEC3 is in sgmii mode.\n");
159 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
160 printf (" eTSEC4 is in sgmii mode.\n");
161
162
163#ifdef CONFIG_PCIE3
164 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
Kumar Gala129ba612008-08-12 11:13:08 -0500166 struct pci_controller *hose = &pcie3_hose;
167 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
168 (host_agent == 5) || (host_agent == 6);
Roy Zang9afc2ef2009-01-09 16:00:55 +0800169 int pcie_configured = (io_sel == 0x7);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500170 struct pci_region *r = hose->regions;
Kumar Gala129ba612008-08-12 11:13:08 -0500171 u32 temp32;
172
Roy Zang028e1162009-01-09 16:01:52 +0800173 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
Kumar Gala129ba612008-08-12 11:13:08 -0500174 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
175 pcie_ep ? "End Point" : "Root Complex",
176 (uint)pci);
177 if (pci->pme_msg_det) {
178 pci->pme_msg_det = 0xffffffff;
179 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
180 }
181 printf ("\n");
182
183 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500184 r += fsl_pci_setup_inbound_windows(r);
Kumar Gala129ba612008-08-12 11:13:08 -0500185
186 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500187 pci_set_region(r++,
Kumar Gala10795f42008-12-02 16:08:36 -0600188 CONFIG_SYS_PCIE3_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 CONFIG_SYS_PCIE3_MEM_PHYS,
190 CONFIG_SYS_PCIE3_MEM_SIZE,
Kumar Gala129ba612008-08-12 11:13:08 -0500191 PCI_REGION_MEM);
192
193 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500194 pci_set_region(r++,
Kumar Gala5f91ef62008-12-02 16:08:37 -0600195 CONFIG_SYS_PCIE3_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 CONFIG_SYS_PCIE3_IO_PHYS,
197 CONFIG_SYS_PCIE3_IO_SIZE,
Kumar Gala129ba612008-08-12 11:13:08 -0500198 PCI_REGION_IO);
199
Kumar Gala2dba0de2008-10-21 08:28:33 -0500200 hose->region_count = r - hose->regions;
Kumar Gala129ba612008-08-12 11:13:08 -0500201 hose->first_busno=first_free_busno;
202 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
203
204 fsl_pci_init(hose);
205
206 first_free_busno=hose->last_busno+1;
207 printf (" PCIE3 on bus %02x - %02x\n",
208 hose->first_busno,hose->last_busno);
209
210 /*
211 * Activate ULI1575 legacy chip by performing a fake
212 * memory access. Needed to make ULI RTC work.
213 * Device 1d has the first on-board memory BAR.
214 */
215
216 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
217 PCI_BASE_ADDRESS_1, &temp32);
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600218 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
Kumar Galaad97dce2009-02-09 22:03:05 -0600219 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
220 temp32, 4, 0);
221 debug(" uli1572 read to %p\n", p);
222 in_be32(p);
Kumar Gala129ba612008-08-12 11:13:08 -0500223 }
224 } else {
225 printf (" PCIE3: disabled\n");
226 }
227
228 }
229#else
230 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
231#endif
232
233#ifdef CONFIG_PCIE2
234 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
Kumar Gala129ba612008-08-12 11:13:08 -0500236 struct pci_controller *hose = &pcie2_hose;
237 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
Ed Swarthout86be5102008-10-09 00:29:27 -0500238 (host_agent == 6) || (host_agent == 0);
Roy Zang9afc2ef2009-01-09 16:00:55 +0800239 int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500240 struct pci_region *r = hose->regions;
Kumar Gala129ba612008-08-12 11:13:08 -0500241
Roy Zang028e1162009-01-09 16:01:52 +0800242 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
Kumar Gala129ba612008-08-12 11:13:08 -0500243 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
244 pcie_ep ? "End Point" : "Root Complex",
245 (uint)pci);
246 if (pci->pme_msg_det) {
247 pci->pme_msg_det = 0xffffffff;
248 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
249 }
250 printf ("\n");
251
252 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500253 r += fsl_pci_setup_inbound_windows(r);
Kumar Gala129ba612008-08-12 11:13:08 -0500254
255 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500256 pci_set_region(r++,
Kumar Gala10795f42008-12-02 16:08:36 -0600257 CONFIG_SYS_PCIE2_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258 CONFIG_SYS_PCIE2_MEM_PHYS,
259 CONFIG_SYS_PCIE2_MEM_SIZE,
Kumar Gala129ba612008-08-12 11:13:08 -0500260 PCI_REGION_MEM);
261
262 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500263 pci_set_region(r++,
Kumar Gala5f91ef62008-12-02 16:08:37 -0600264 CONFIG_SYS_PCIE2_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 CONFIG_SYS_PCIE2_IO_PHYS,
266 CONFIG_SYS_PCIE2_IO_SIZE,
Kumar Gala129ba612008-08-12 11:13:08 -0500267 PCI_REGION_IO);
268
Kumar Gala2dba0de2008-10-21 08:28:33 -0500269 hose->region_count = r - hose->regions;
Kumar Gala129ba612008-08-12 11:13:08 -0500270 hose->first_busno=first_free_busno;
271 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
272
273 fsl_pci_init(hose);
274 first_free_busno=hose->last_busno+1;
275 printf (" PCIE2 on bus %02x - %02x\n",
276 hose->first_busno,hose->last_busno);
277
278 } else {
279 printf (" PCIE2: disabled\n");
280 }
281
282 }
283#else
284 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
285#endif
286#ifdef CONFIG_PCIE1
287 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
Kumar Gala129ba612008-08-12 11:13:08 -0500289 struct pci_controller *hose = &pcie1_hose;
Ed Swarthout86be5102008-10-09 00:29:27 -0500290 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
Kumar Gala129ba612008-08-12 11:13:08 -0500291 (host_agent == 5);
Roy Zang9afc2ef2009-01-09 16:00:55 +0800292 int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
293 (io_sel == 0x7) || (io_sel == 0xb) ||
294 (io_sel == 0xc) || (io_sel == 0xf);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500295 struct pci_region *r = hose->regions;
Kumar Gala129ba612008-08-12 11:13:08 -0500296
297 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
298 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
299 pcie_ep ? "End Point" : "Root Complex",
300 (uint)pci);
301 if (pci->pme_msg_det) {
302 pci->pme_msg_det = 0xffffffff;
303 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
304 }
305 printf ("\n");
306
307 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500308 r += fsl_pci_setup_inbound_windows(r);
Kumar Gala129ba612008-08-12 11:13:08 -0500309
310 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500311 pci_set_region(r++,
Kumar Gala10795f42008-12-02 16:08:36 -0600312 CONFIG_SYS_PCIE1_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313 CONFIG_SYS_PCIE1_MEM_PHYS,
314 CONFIG_SYS_PCIE1_MEM_SIZE,
Kumar Gala129ba612008-08-12 11:13:08 -0500315 PCI_REGION_MEM);
316
317 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500318 pci_set_region(r++,
Kumar Gala5f91ef62008-12-02 16:08:37 -0600319 CONFIG_SYS_PCIE1_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320 CONFIG_SYS_PCIE1_IO_PHYS,
321 CONFIG_SYS_PCIE1_IO_SIZE,
Kumar Gala129ba612008-08-12 11:13:08 -0500322 PCI_REGION_IO);
323
Kumar Gala2dba0de2008-10-21 08:28:33 -0500324 hose->region_count = r - hose->regions;
Kumar Gala129ba612008-08-12 11:13:08 -0500325 hose->first_busno=first_free_busno;
326
327 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
328
329 fsl_pci_init(hose);
330
331 first_free_busno=hose->last_busno+1;
332 printf(" PCIE1 on bus %02x - %02x\n",
333 hose->first_busno,hose->last_busno);
334
335 } else {
336 printf (" PCIE1: disabled\n");
337 }
338
339 }
340#else
341 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
342#endif
343}
344#endif
345
346int board_early_init_r(void)
347{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
Kumar Gala129ba612008-08-12 11:13:08 -0500349 const u8 flash_esel = 2;
350
351 /*
352 * Remap Boot flash + PROMJET region to caching-inhibited
353 * so that flash can be erased properly.
354 */
355
Kumar Gala7c0d4a72008-09-22 14:11:11 -0500356 /* Flush d-cache and invalidate i-cache of any FLASH data */
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100357 flush_dcache();
358 invalidate_icache();
Kumar Gala129ba612008-08-12 11:13:08 -0500359
360 /* invalidate existing TLB entry for flash + promjet */
361 disable_tlb(flash_esel);
362
Kumar Galac953ddf2008-12-02 14:19:34 -0600363 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
Kumar Gala129ba612008-08-12 11:13:08 -0500364 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
365 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
366
367 return 0;
368}
369
370#ifdef CONFIG_GET_CLK_FROM_ICS307
371/* decode S[0-2] to Output Divider (OD) */
372static unsigned char ics307_S_to_OD[] = {
373 10, 2, 8, 4, 5, 7, 3, 6
374};
375
376/* Calculate frequency being generated by ICS307-02 clock chip based upon
377 * the control bytes being programmed into it. */
378/* XXX: This function should probably go into a common library */
379static unsigned long
380ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
381{
382 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
383 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
384 unsigned long RDW = cw2 & 0x7F;
385 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
386 unsigned long freq;
387
388 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
389
390 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
391 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
392 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
393 *
394 * R6:R0 = Reference Divider Word (RDW)
395 * V8:V0 = VCO Divider Word (VDW)
396 * S2:S0 = Output Divider Select (OD)
397 * F1:F0 = Function of CLK2 Output
398 * TTL = duty cycle
399 * C1:C0 = internal load capacitance for cyrstal
400 */
401
402 /* Adding 1 to get a "nicely" rounded number, but this needs
403 * more tweaking to get a "properly" rounded number. */
404
405 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
406
407 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
408 freq);
409 return freq;
410}
411
412unsigned long get_board_sys_clk(ulong dummy)
413{
414 return ics307_clk_freq (
415 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
416 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
417 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
418 );
419}
420
421unsigned long get_board_ddr_clk(ulong dummy)
422{
423 return ics307_clk_freq (
424 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
425 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
426 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
427 );
428}
429#else
430unsigned long get_board_sys_clk(ulong dummy)
431{
432 u8 i;
433 ulong val = 0;
434
435 i = in8(PIXIS_BASE + PIXIS_SPD);
436 i &= 0x07;
437
438 switch (i) {
439 case 0:
440 val = 33333333;
441 break;
442 case 1:
443 val = 40000000;
444 break;
445 case 2:
446 val = 50000000;
447 break;
448 case 3:
449 val = 66666666;
450 break;
451 case 4:
452 val = 83333333;
453 break;
454 case 5:
455 val = 100000000;
456 break;
457 case 6:
458 val = 133333333;
459 break;
460 case 7:
461 val = 166666666;
462 break;
463 }
464
465 return val;
466}
467
468unsigned long get_board_ddr_clk(ulong dummy)
469{
470 u8 i;
471 ulong val = 0;
472
473 i = in8(PIXIS_BASE + PIXIS_SPD);
474 i &= 0x38;
475 i >>= 3;
476
477 switch (i) {
478 case 0:
479 val = 33333333;
480 break;
481 case 1:
482 val = 40000000;
483 break;
484 case 2:
485 val = 50000000;
486 break;
487 case 3:
488 val = 66666666;
489 break;
490 case 4:
491 val = 83333333;
492 break;
493 case 5:
494 val = 100000000;
495 break;
496 case 6:
497 val = 133333333;
498 break;
499 case 7:
500 val = 166666666;
501 break;
502 }
503 return val;
504}
505#endif
506
Liu Yu7e183ca2008-10-10 11:40:59 +0800507#ifdef CONFIG_TSEC_ENET
508int board_eth_init(bd_t *bis)
509{
510 struct tsec_info_struct tsec_info[4];
511 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
512 int num = 0;
513
514#ifdef CONFIG_TSEC1
515 SET_STD_TSEC_INFO(tsec_info[num], 1);
516 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
517 tsec_info[num].flags |= TSEC_SGMII;
518 num++;
519#endif
520#ifdef CONFIG_TSEC2
521 SET_STD_TSEC_INFO(tsec_info[num], 2);
522 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
523 tsec_info[num].flags |= TSEC_SGMII;
524 num++;
525#endif
526#ifdef CONFIG_TSEC3
527 SET_STD_TSEC_INFO(tsec_info[num], 3);
528 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
529 tsec_info[num].flags |= TSEC_SGMII;
530 num++;
531#endif
532#ifdef CONFIG_TSEC4
533 SET_STD_TSEC_INFO(tsec_info[num], 4);
534 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
535 tsec_info[num].flags |= TSEC_SGMII;
536 num++;
537#endif
538
539 if (!num) {
540 printf("No TSECs initialized\n");
541
542 return 0;
543 }
544
545 fsl_sgmii_riser_init(tsec_info, num);
546
547 tsec_eth_init(bis, tsec_info, num);
548
549 return 0;
550}
551#endif
552
Kumar Gala129ba612008-08-12 11:13:08 -0500553#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500554extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100555 struct pci_controller *hose);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500556
Kumar Gala129ba612008-08-12 11:13:08 -0500557void ft_board_setup(void *blob, bd_t *bd)
558{
Kumar Gala129ba612008-08-12 11:13:08 -0500559 ulong base, size;
560
561 ft_cpu_setup(blob, bd);
562
563 base = getenv_bootm_low();
564 size = getenv_bootm_size();
565
566 fdt_fixup_memory(blob, (u64)base, (u64)size);
567
Kumar Gala129ba612008-08-12 11:13:08 -0500568#ifdef CONFIG_PCIE3
Kumar Gala2dba0de2008-10-21 08:28:33 -0500569 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
Kumar Gala129ba612008-08-12 11:13:08 -0500570#endif
571#ifdef CONFIG_PCIE2
Kumar Gala2dba0de2008-10-21 08:28:33 -0500572 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
Kumar Gala129ba612008-08-12 11:13:08 -0500573#endif
574#ifdef CONFIG_PCIE1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500575 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
Kumar Gala129ba612008-08-12 11:13:08 -0500576#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500577}
578#endif
579
580#ifdef CONFIG_MP
581extern void cpu_mp_lmb_reserve(struct lmb *lmb);
582
583void board_lmb_reserve(struct lmb *lmb)
584{
585 cpu_mp_lmb_reserve(lmb);
586}
587#endif