| Alexey Brodkin | 288aaac | 2014-02-04 12:56:13 +0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARC_ARCREGS_H |
| 8 | #define _ASM_ARC_ARCREGS_H |
| 9 | |
| Alexey Brodkin | 812980b | 2015-02-03 13:58:11 +0300 | [diff] [blame] | 10 | #include <asm/cache.h> |
| 11 | |
| Alexey Brodkin | 288aaac | 2014-02-04 12:56:13 +0400 | [diff] [blame] | 12 | /* |
| 13 | * ARC architecture has additional address space - auxiliary registers. |
| 14 | * These registers are mostly used for configuration purposes. |
| 15 | * These registers are not memory mapped and special commands are used for |
| 16 | * access: "lr"/"sr". |
| 17 | */ |
| 18 | |
| 19 | #define ARC_AUX_IDENTITY 0x04 |
| 20 | #define ARC_AUX_STATUS32 0x0a |
| 21 | |
| 22 | /* Instruction cache related auxiliary registers */ |
| 23 | #define ARC_AUX_IC_IVIC 0x10 |
| 24 | #define ARC_AUX_IC_CTRL 0x11 |
| 25 | #define ARC_AUX_IC_IVIL 0x19 |
| Alexey Brodkin | 5ff40f3 | 2015-02-03 13:58:12 +0300 | [diff] [blame] | 26 | #if (CONFIG_ARC_MMU_VER == 3) |
| Alexey Brodkin | 288aaac | 2014-02-04 12:56:13 +0400 | [diff] [blame] | 27 | #define ARC_AUX_IC_PTAG 0x1E |
| 28 | #endif |
| Igor Guryanov | f8cf3d1 | 2014-12-24 16:07:07 +0300 | [diff] [blame] | 29 | #define ARC_BCR_IC_BUILD 0x77 |
| Alexey Brodkin | 288aaac | 2014-02-04 12:56:13 +0400 | [diff] [blame] | 30 | |
| 31 | /* Timer related auxiliary registers */ |
| 32 | #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ |
| 33 | #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ |
| 34 | #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ |
| 35 | |
| 36 | #define ARC_AUX_INTR_VEC_BASE 0x25 |
| 37 | |
| 38 | /* Data cache related auxiliary registers */ |
| 39 | #define ARC_AUX_DC_IVDC 0x47 |
| 40 | #define ARC_AUX_DC_CTRL 0x48 |
| 41 | |
| 42 | #define ARC_AUX_DC_IVDL 0x4A |
| 43 | #define ARC_AUX_DC_FLSH 0x4B |
| 44 | #define ARC_AUX_DC_FLDL 0x4C |
| Alexey Brodkin | 5ff40f3 | 2015-02-03 13:58:12 +0300 | [diff] [blame] | 45 | #if (CONFIG_ARC_MMU_VER == 3) |
| Alexey Brodkin | 288aaac | 2014-02-04 12:56:13 +0400 | [diff] [blame] | 46 | #define ARC_AUX_DC_PTAG 0x5C |
| 47 | #endif |
| Igor Guryanov | f8cf3d1 | 2014-12-24 16:07:07 +0300 | [diff] [blame] | 48 | #define ARC_BCR_DC_BUILD 0x72 |
| Alexey Brodkin | 6eb15e5 | 2015-03-30 13:36:04 +0300 | [diff] [blame] | 49 | #define ARC_BCR_SLC 0xce |
| Alexey Brodkin | ef639e6 | 2015-05-18 16:56:26 +0300 | [diff] [blame] | 50 | #define ARC_AUX_SLC_CONFIG 0x901 |
| 51 | #define ARC_AUX_SLC_CTRL 0x903 |
| Alexey Brodkin | 6eb15e5 | 2015-03-30 13:36:04 +0300 | [diff] [blame] | 52 | #define ARC_AUX_SLC_FLUSH 0x904 |
| 53 | #define ARC_AUX_SLC_INVALIDATE 0x905 |
| Alexey Brodkin | ef639e6 | 2015-05-18 16:56:26 +0300 | [diff] [blame] | 54 | #define ARC_AUX_SLC_IVDL 0x910 |
| 55 | #define ARC_AUX_SLC_FLDL 0x912 |
| Alexey Brodkin | db6ce23 | 2015-12-14 17:15:13 +0300 | [diff] [blame] | 56 | #define ARC_BCR_CLUSTER 0xcf |
| 57 | |
| 58 | /* IO coherency related auxiliary registers */ |
| 59 | #define ARC_AUX_IO_COH_ENABLE 0x500 |
| 60 | #define ARC_AUX_IO_COH_PARTIAL 0x501 |
| 61 | #define ARC_AUX_IO_COH_AP0_BASE 0x508 |
| 62 | #define ARC_AUX_IO_COH_AP0_SIZE 0x509 |
| Alexey Brodkin | 288aaac | 2014-02-04 12:56:13 +0400 | [diff] [blame] | 63 | |
| 64 | #ifndef __ASSEMBLY__ |
| 65 | /* Accessors for auxiliary registers */ |
| 66 | #define read_aux_reg(reg) __builtin_arc_lr(reg) |
| 67 | |
| 68 | /* gcc builtin sr needs reg param to be long immediate */ |
| 69 | #define write_aux_reg(reg_immed, val) \ |
| 70 | __builtin_arc_sr((unsigned int)val, reg_immed) |
| 71 | #endif /* __ASSEMBLY__ */ |
| 72 | |
| 73 | #endif /* _ASM_ARC_ARCREGS_H */ |