| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 1 | CONFIG_X86=y |
| 2 | CONFIG_VENDOR_INTEL=y | ||||
| 3 | CONFIG_DEFAULT_DEVICE_TREE="bayleybay" | ||||
| 4 | CONFIG_TARGET_BAYLEYBAY=y | ||||
| 5 | CONFIG_HAVE_INTEL_ME=y | ||||
| Bin Meng | 638a058 | 2015-10-11 21:37:44 -0700 | [diff] [blame] | 6 | CONFIG_ENABLE_MRC_CACHE=y |
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 7 | CONFIG_SMP=y |
| 8 | CONFIG_HAVE_VGA_BIOS=y | ||||
| Bin Meng | cc6ae97 | 2015-08-27 08:38:17 -0700 | [diff] [blame] | 9 | CONFIG_VGA_BIOS_ADDR=0xfffa0000 |
| Bin Meng | fe3fbd3 | 2015-07-30 03:49:18 -0700 | [diff] [blame] | 10 | CONFIG_GENERATE_PIRQ_TABLE=y |
| 11 | CONFIG_GENERATE_MP_TABLE=y | ||||
| Simon Glass | 73223f0 | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 12 | CONFIG_FIT=y |
| Simon Glass | 4edb945 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 13 | CONFIG_BOOTSTAGE=y |
| 14 | CONFIG_BOOTSTAGE_REPORT=y | ||||
| Tom Rini | adad96e | 2016-04-21 21:37:19 -0400 | [diff] [blame^] | 15 | CONFIG_HUSH_PARSER=y |
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 16 | CONFIG_CMD_CPU=y |
| 17 | # CONFIG_CMD_IMLS is not set | ||||
| 18 | # CONFIG_CMD_FLASH is not set | ||||
| Thomas Chou | e4aa8ed | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 19 | CONFIG_CMD_GPIO=y |
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 20 | # CONFIG_CMD_SETEXPR is not set |
| 21 | # CONFIG_CMD_NFS is not set | ||||
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 22 | CONFIG_CMD_BOOTSTAGE=y |
| 23 | CONFIG_OF_CONTROL=y | ||||
| Simon Glass | 15cf75e | 2016-03-11 22:07:14 -0700 | [diff] [blame] | 24 | CONFIG_REGMAP=y |
| 25 | CONFIG_SYSCON=y | ||||
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 26 | CONFIG_CPU=y |
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 27 | CONFIG_SPI_FLASH=y |
| Bin Meng | 68d5342 | 2015-11-25 05:34:54 -0800 | [diff] [blame] | 28 | CONFIG_SPI_FLASH_GIGADEVICE=y |
| 29 | CONFIG_SPI_FLASH_MACRONIX=y | ||||
| 30 | CONFIG_SPI_FLASH_WINBOND=y | ||||
| Bin Meng | 468e81c | 2015-08-28 02:22:39 -0700 | [diff] [blame] | 31 | CONFIG_DM_ETH=y |
| Simon Glass | a77fda1 | 2015-08-19 09:33:43 -0600 | [diff] [blame] | 32 | CONFIG_E1000=y |
| Bin Meng | 80df691 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 33 | CONFIG_DM_PCI=y |
| 34 | CONFIG_DM_RTC=y | ||||
| Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 35 | CONFIG_SYS_NS16550=y |
| Bin Meng | e5d5d44 | 2015-11-25 05:34:53 -0800 | [diff] [blame] | 36 | CONFIG_ICH_SPI=y |
| Bin Meng | 80af398 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 37 | CONFIG_TIMER=y |
| Bin Meng | 80df691 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 38 | CONFIG_USB=y |
| 39 | CONFIG_DM_USB=y | ||||
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 40 | CONFIG_VIDEO_VESA=y |
| 41 | CONFIG_FRAMEBUFFER_SET_VESA_MODE=y | ||||
| 42 | CONFIG_FRAMEBUFFER_VESA_MODE_11A=y | ||||
| Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 43 | CONFIG_USE_PRIVATE_LIBGCC=y |