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wdenk79fa88f2004-06-07 23:46:25 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
33#error Unsupported CONFIG_NETTA2 version
34#endif
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
42#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */
43
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47
48#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49
50/* #define CONFIG_XIN 10000000 */
51#define CONFIG_XIN 50000000
52/* #define MPC8XX_HZ 120000000 */
53#define MPC8XX_HZ 66666666
54
55#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56
57#if 0
58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62
63#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
64
65#define CONFIG_PREBOOT "echo;"
66
67#undef CONFIG_BOOTARGS
68#define CONFIG_BOOTCOMMAND \
69 "tftpboot; " \
70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
72 "bootm"
73
74#define CONFIG_AUTOSCRIPT
75#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
76#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
77
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
84
85#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
86
87#undef CONFIG_MAC_PARTITION
88#undef CONFIG_DOS_PARTITION
89
90#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
91
92#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
93#define FEC_ENET 1 /* eth.c needs it that way... */
94#undef CFG_DISCOVER_PHY
95#define CONFIG_MII 1
96#define CONFIG_RMII 1 /* use RMII interface */
97
98#define CONFIG_ETHER_ON_FEC1 1
99#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
100#define CONFIG_FEC1_PHY_NORXERR 1
101
102#define CONFIG_ETHER_ON_FEC2 1
103#define CONFIG_FEC2_PHY 4
104#define CONFIG_FEC2_PHY_NORXERR 1
105
106#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
107
108#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
109 CFG_CMD_NAND | \
110 CFG_CMD_DHCP | \
111 CFG_CMD_PING | \
112 CFG_CMD_MII | \
113 CFG_CMD_CDP \
114 )
115
116#define CONFIG_BOARD_EARLY_INIT_F 1
117#define CONFIG_MISC_INIT_R
118
119/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120#include <cmd_confdefs.h>
121
122/*
123 * Miscellaneous configurable options
124 */
125#define CFG_LONGHELP /* undef to save memory */
126#define CFG_PROMPT "=> " /* Monitor Command Prompt */
127
128#define CFG_HUSH_PARSER 1
129#define CFG_PROMPT_HUSH_PS2 "> "
130
131#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
132#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
133#else
134#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
135#endif
136#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
137#define CFG_MAXARGS 16 /* max number of command args */
138#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
139
140#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
141#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
142
143#define CFG_LOAD_ADDR 0x100000 /* default load address */
144
145#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
146
147#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
148
149/*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
154/*-----------------------------------------------------------------------
155 * Internal Memory Mapped Register
156 */
157#define CFG_IMMR 0xFF000000
158
159/*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
161 */
162#define CFG_INIT_RAM_ADDR CFG_IMMR
163#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
164#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
165#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
166#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
171 * Please note that CFG_SDRAM_BASE _must_ start at 0
172 */
173#define CFG_SDRAM_BASE 0x00000000
174#define CFG_FLASH_BASE 0x40000000
175#if defined(DEBUG)
176#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177#else
178#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
179#endif
180#define CFG_MONITOR_BASE CFG_FLASH_BASE
181#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
182#if CONFIG_NETTA2_VERSION == 2
183#define CFG_FLASH_BASE4 0x40080000
184#endif
185
186#define CFG_RESET_ADDRESS 0x80000000
187
188/*
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
192 */
193#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
194
195/*-----------------------------------------------------------------------
196 * FLASH organization
197 */
198#if CONFIG_NETTA2_VERSION == 1
199#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
200#elif CONFIG_NETTA2_VERSION == 2
201#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
202#endif
203#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
204
205#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
206#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
207
208#define CFG_ENV_IS_IN_FLASH 1
209#define CFG_ENV_SECT_SIZE 0x10000
210
211#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
212#define CFG_ENV_OFFSET 0
213#define CFG_ENV_SIZE 0x4000
214
215#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
216#define CFG_ENV_OFFSET_REDUND 0
217#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
218
219/*-----------------------------------------------------------------------
220 * Cache Configuration
221 */
222#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
223#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
224#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
225#endif
226
227/*-----------------------------------------------------------------------
228 * SYPCR - System Protection Control 11-9
229 * SYPCR can only be written once after reset!
230 *-----------------------------------------------------------------------
231 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
232 */
233#if defined(CONFIG_WATCHDOG)
234#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
235 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
236#else
237#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
238#endif
239
240/*-----------------------------------------------------------------------
241 * SIUMCR - SIU Module Configuration 11-6
242 *-----------------------------------------------------------------------
243 * PCMCIA config., multi-function pin tri-state
244 */
245#ifndef CONFIG_CAN_DRIVER
246#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
247#else /* we must activate GPL5 in the SIUMCR for CAN */
248#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
249#endif /* CONFIG_CAN_DRIVER */
250
251/*-----------------------------------------------------------------------
252 * TBSCR - Time Base Status and Control 11-26
253 *-----------------------------------------------------------------------
254 * Clear Reference Interrupt Status, Timebase freezing enabled
255 */
256#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
257
258/*-----------------------------------------------------------------------
259 * RTCSC - Real-Time Clock Status and Control Register 11-27
260 *-----------------------------------------------------------------------
261 */
262#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263
264/*-----------------------------------------------------------------------
265 * PISCR - Periodic Interrupt Status and Control 11-31
266 *-----------------------------------------------------------------------
267 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268 */
269#define CFG_PISCR (PISCR_PS | PISCR_PITF)
270
271/*-----------------------------------------------------------------------
272 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
273 *-----------------------------------------------------------------------
274 * Reset PLL lock status sticky bit, timer expired status bit and timer
275 * interrupt status bit
276 *
277 */
278
279#if CONFIG_XIN == 10000000
280
281#if MPC8XX_HZ == 120000000
282#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
283 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
284 PLPRCR_TEXPS)
285#elif MPC8XX_HZ == 100000000
286#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
287 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
288 PLPRCR_TEXPS)
289#elif MPC8XX_HZ == 50000000
290#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
291 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
292 PLPRCR_TEXPS)
293#elif MPC8XX_HZ == 25000000
294#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
295 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
296 PLPRCR_TEXPS)
297#elif MPC8XX_HZ == 40000000
298#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
299 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
300 PLPRCR_TEXPS)
301#elif MPC8XX_HZ == 75000000
302#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
303 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
304 PLPRCR_TEXPS)
305#else
306#error unsupported CPU freq for XIN = 10MHz
307#endif
308
309#elif CONFIG_XIN == 50000000
310
311#if MPC8XX_HZ == 120000000
312#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
313 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
314 PLPRCR_TEXPS)
315#elif MPC8XX_HZ == 100000000
316#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
317 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
318 PLPRCR_TEXPS)
319#elif MPC8XX_HZ == 66666666
320#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
321 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
322 PLPRCR_TEXPS)
323#else
324#error unsupported CPU freq for XIN = 50MHz
325#endif
326
327#else
328
329#error unsupported XIN freq
330#endif
331
332
333/*
334 *-----------------------------------------------------------------------
335 * SCCR - System Clock and reset Control Register 15-27
336 *-----------------------------------------------------------------------
337 * Set clock output, timebase and RTC source and divider,
338 * power management and some other internal clocks
339 *
340 * Note: When TBS == 0 the timebase is independent of current cpu clock.
341 */
342
343#define SCCR_MASK SCCR_EBDF11
344#if MPC8XX_HZ > 66666666
345#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
346 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
347 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
348 SCCR_DFALCD00 | SCCR_EBDF01)
349#else
350#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
351 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
352 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
353 SCCR_DFALCD00)
354#endif
355
356/*-----------------------------------------------------------------------
357 *
358 *-----------------------------------------------------------------------
359 *
360 */
361/*#define CFG_DER 0x2002000F*/
362#define CFG_DER 0
363
364/*
365 * Init Memory Controller:
366 *
367 * BR0/1 and OR0/1 (FLASH)
368 */
369
370#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
371
372/* used to re-map FLASH both when starting from SRAM or FLASH:
373 * restrict access enough to keep SRAM working (if any)
374 * but not too much to meddle with FLASH accesses
375 */
376#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
377#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
378
379/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
380#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
381
382#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
383#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
384#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
385
386#if CONFIG_NETTA2_VERSION == 2
387
388#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
389
390#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
391#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
392#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
393
394#endif
395
396/*
397 * BR3 and OR3 (SDRAM)
398 *
399 */
400#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
401#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
402
403/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
404#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
405
406#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
407#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
408
409/*
410 * Memory Periodic Timer Prescaler
411 */
412
413/*
414 * Memory Periodic Timer Prescaler
415 *
416 * The Divider for PTA (refresh timer) configuration is based on an
417 * example SDRAM configuration (64 MBit, one bank). The adjustment to
418 * the number of chip selects (NCS) and the actually needed refresh
419 * rate is done by setting MPTPR.
420 *
421 * PTA is calculated from
422 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
423 *
424 * gclk CPU clock (not bus clock!)
425 * Trefresh Refresh cycle * 4 (four word bursts used)
426 *
427 * 4096 Rows from SDRAM example configuration
428 * 1000 factor s -> ms
429 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
430 * 4 Number of refresh cycles per period
431 * 64 Refresh cycle in ms per number of rows
432 * --------------------------------------------
433 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
434 *
435 * 50 MHz => 50.000.000 / Divider = 98
436 * 66 Mhz => 66.000.000 / Divider = 129
437 * 80 Mhz => 80.000.000 / Divider = 156
438 */
439
440#define CFG_MAMR_PTA 234
441
442/*
443 * For 16 MBit, refresh rates could be 31.3 us
444 * (= 64 ms / 2K = 125 / quad bursts).
445 * For a simpler initialization, 15.6 us is used instead.
446 *
447 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
448 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
449 */
450#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
451#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
452
453/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
454#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
455#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
456
457/*
458 * MAMR settings for SDRAM
459 */
460
461/* 8 column SDRAM */
462#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
463 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465
466/* 9 column SDRAM */
467#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
468 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
470
471/*
472 * Internal Definitions
473 *
474 * Boot Flags
475 */
476#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
477#define BOOTFLAG_WARM 0x02 /* Software reboot */
478
479#define CONFIG_ARTOS /* include ARTOS support */
480
481#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
482
483/****************************************************************/
484
485#define DSP_SIZE 0x00010000 /* 64K */
486#define NAND_SIZE 0x00010000 /* 64K */
487
488#define DSP_BASE 0xF1000000
489#define NAND_BASE 0xF1010000
490
491/****************************************************************/
492
493/* NAND */
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100494#define CFG_NAND_LEGACY
wdenk79fa88f2004-06-07 23:46:25 +0000495#define CFG_NAND_BASE NAND_BASE
496#define CONFIG_MTD_NAND_ECC_JFFS2
497#define CONFIG_MTD_NAND_VERIFY_WRITE
498#define CONFIG_MTD_NAND_UNSAFE
499
500#define CFG_MAX_NAND_DEVICE 1
501
502#define SECTORSIZE 512
503#define ADDR_COLUMN 1
504#define ADDR_PAGE 2
505#define ADDR_COLUMN_PAGE 3
506#define NAND_ChipID_UNKNOWN 0x00
507#define NAND_MAX_FLOORS 1
508#define NAND_MAX_CHIPS 1
509
510/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
511#define NAND_DISABLE_CE(nand) \
512 do { \
513 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
514 } while(0)
515
516#define NAND_ENABLE_CE(nand) \
517 do { \
518 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
519 } while(0)
520
521#define NAND_CTL_CLRALE(nandptr) \
522 do { \
523 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
524 } while(0)
525
526#define NAND_CTL_SETALE(nandptr) \
527 do { \
528 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
529 } while(0)
530
531#define NAND_CTL_CLRCLE(nandptr) \
532 do { \
533 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
534 } while(0)
535
536#define NAND_CTL_SETCLE(nandptr) \
537 do { \
538 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
539 } while(0)
540
541#if CONFIG_NETTA2_VERSION == 1
542#define NAND_WAIT_READY(nand) \
543 do { \
544 int _tries = 0; \
545 while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
546 if (++_tries > 100000) \
547 break; \
548 } while (0)
549#elif CONFIG_NETTA2_VERSION == 2
550#define NAND_WAIT_READY(nand) \
551 do { \
552 int _tries = 0; \
553 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
554 if (++_tries > 100000) \
555 break; \
556 } while (0)
557#endif
558
559#define WRITE_NAND_COMMAND(d, adr) \
560 do { \
561 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
562 } while(0)
563
564#define WRITE_NAND_ADDRESS(d, adr) \
565 do { \
566 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
567 } while(0)
568
569#define WRITE_NAND(d, adr) \
570 do { \
571 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
572 } while(0)
573
574#define READ_NAND(adr) \
575 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
576
577/*****************************************************************************/
578
579#define CFG_DIRECT_FLASH_TFTP
580#define CFG_DIRECT_NAND_TFTP
581
582/*****************************************************************************/
583
584#if CONFIG_NETTA2_VERSION == 1
585#define STATUS_LED_BIT 0x00000008 /* bit 28 */
586#elif CONFIG_NETTA2_VERSION == 2
587#define STATUS_LED_BIT 0x00000080 /* bit 24 */
588#endif
589
590#define STATUS_LED_PERIOD (CFG_HZ / 2)
591#define STATUS_LED_STATE STATUS_LED_BLINKING
592
593#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
594#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
595
596#ifndef __ASSEMBLY__
597
598/* LEDs */
599
600/* led_id_t is unsigned int mask */
601typedef unsigned int led_id_t;
602
603#define __led_toggle(_msk) \
604 do { \
605 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
606 } while(0)
607
608#define __led_set(_msk, _st) \
609 do { \
610 if ((_st)) \
611 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
612 else \
613 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
614 } while(0)
615
616#define __led_init(msk, st) __led_set(msk, st)
617
618#endif
619
620/***********************************************************************************************************
621
622 ----------------------------------------------------------------------------------------------
623
624 (V1) version 1 of the board
625 (V2) version 2 of the board
626
627 ----------------------------------------------------------------------------------------------
628
629 Pin definitions:
630
631 +------+----------------+--------+------------------------------------------------------------
632 | # | Name | Type | Comment
633 +------+----------------+--------+------------------------------------------------------------
634 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
635 | PA7 | DSP_INT | Output | DSP interrupt
636 | PA10 | DSP_RESET | Output | DSP reset
637 | PA14 | USBOE | Output | USB (1)
638 | PA15 | USBRXD | Output | USB (1)
639 | PB19 | BT_RTS | Output | Bluetooth (0)
640 | PB23 | BT_CTS | Output | Bluetooth (0)
641 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
642 | PB27 | SPICS_DISP | Output | Display chip select
643 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
644 | PB29 | SPI_TXD | Output | SPI Data Tx
645 | PB30 | SPI_CLK | Output | SPI Clock
646 | PC10 | DISPA0 | Output | Display A0
647 | PC11 | BACKLIGHT | Output | Display backlit
648 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
649 | | IO_RESET | Output | (V2) General I/O reset
650 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
651 | | HOOK | Input | (V2) Hook input interrupt
652 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
653 | | F_RY_BY | Input | (V2) NAND F_RY_BY
654 | PE17 | F_ALE | Output | NAND F_ALE
655 | PE18 | F_CLE | Output | NAND F_CLE
656 | PE20 | F_CE | Output | NAND F_CE
657 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
658 | | LED | Output | (V2) LED
659 | PE27 | SPICS_ER | Output | External serial register CS
660 | PE28 | LEDIO1 | Output | (V1) LED
661 | | BKBR1 | Input | (V2) Keyboard input scan
662 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
663 | | BKBR2 | Input | (V2) Keyboard input scan
664 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
665 | | BKBR3 | Input | (V2) Keyboard input scan
666 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
667 | | BKBR4 | Input | (V2) Keyboard input scan
668 +------+----------------+--------+---------------------------------------------------
669
670 ----------------------------------------------------------------------------------------------
671
672 Serial register input:
673
674 +------+----------------+------------------------------------------------------------
675 | # | Name | Comment
676 +------+----------------+------------------------------------------------------------
677 | 4 | HOOK | Hook switch
678 | 5 | BT_LINK | Bluetooth link status
679 | 6 | HOST_WAKE | Bluetooth host wake up
680 | 7 | OK_ETH | Cisco inline power OK status
681 +------+----------------+------------------------------------------------------------
682
683 ----------------------------------------------------------------------------------------------
684
685 Chip selects:
686
687 +------+----------------+------------------------------------------------------------
688 | # | Name | Comment
689 +------+----------------+------------------------------------------------------------
690 | CS0 | CS0 | Boot flash
691 | CS1 | CS_FLASH | NAND flash
692 | CS2 | CS_DSP | DSP
693 | CS3 | DCS_DRAM | DRAM
694 | CS4 | CS_FLASH2 | (V2) 2nd flash
695 +------+----------------+------------------------------------------------------------
696
697 ----------------------------------------------------------------------------------------------
698
699 Interrupts:
700
701 +------+----------------+------------------------------------------------------------
702 | # | Name | Comment
703 +------+----------------+------------------------------------------------------------
704 | IRQ1 | IRQ_DSP | DSP interrupt
705 | IRQ3 | S_INTER | DUSLIC ???
706 | IRQ4 | F_RY_BY | NAND
707 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
708 +------+----------------+------------------------------------------------------------
709
710 ----------------------------------------------------------------------------------------------
711
712 Interrupts on PCMCIA pins:
713
714 +------+----------------+------------------------------------------------------------
715 | # | Name | Comment
716 +------+----------------+------------------------------------------------------------
717 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
718 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
719 | IP_A2| RMII1_MDINT | PHY interrupt for #1
720 | IP_A3| RMII2_MDINT | PHY interrupt for #2
721 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
722 | IP_A6| OK_ETH | (V2) Cisco inline power OK
723 +------+----------------+------------------------------------------------------------
724
725**************************************************************************************************/
726
727#define CFG_CONSOLE_IS_IN_ENV 1
728#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
729#define CFG_CONSOLE_ENV_OVERWRITE 1
730
731/*************************************************************************************************/
732
733/* use board specific hardware */
734#undef CONFIG_WATCHDOG /* watchdog disabled */
735#define CONFIG_HW_WATCHDOG
736#define CONFIG_SHOW_ACTIVITY
737
738/*************************************************************************************************/
739
740#define CONFIG_CDP_DEVICE_ID 20
741#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */
742#define CONFIG_CDP_PORT_ID "eth%d"
743#define CONFIG_CDP_CAPABILITIES 0x00000010
744#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__
745#define CONFIG_CDP_PLATFORM "Intracom NetTA2"
746#define CONFIG_CDP_TRIGGER 0x20020001
747#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
748#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */
749
750/*************************************************************************************************/
751
752#define CONFIG_AUTO_COMPLETE 1
753
754/*************************************************************************************************/
755
756#define CONFIG_CRC32_VERIFY 1
757
758/*************************************************************************************************/
759
760#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
761
762/*************************************************************************************************/
763#endif /* __CONFIG_H */