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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / adfaa4284c0941161baa191b35e3a866c6d5ef4d / . / include / configs / hsdk-4xd.h
blob: d3d8896ecff1b1b72d45b121efd47bac4dc3fcd4 [file] [log] [blame]
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
5 */
6
7#ifndef _CONFIG_HSDK_H_
8#define _CONFIG_HSDK_H_
9
10#include <linux/sizes.h>
11
12/*
13 * CPU configuration
14 */
15#define NR_CPUS 4
16#define ARC_PERIPHERAL_BASE 0xF0000000
17#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
18#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
19
20/*
21 * Memory configuration
22 */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]23
24#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26#define CONFIG_SYS_SDRAM_SIZE SZ_1G
27
28#define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
30
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]31#define CONFIG_SYS_BOOTM_LEN SZ_128M
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]32
33/*
34 * UART configuration
35 */
36#define CONFIG_SYS_NS16550_SERIAL
37#define CONFIG_SYS_NS16550_CLK 33330000
38#define CONFIG_SYS_NS16550_MEM32
39
40/*
41 * Ethernet PHY configuration
42 */
43
44/*
45 * USB 1.1 configuration
46 */
47#define CONFIG_USB_OHCI_NEW
48#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
49
50/*
51 * Environment settings
52 */
53#define CONFIG_EXTRA_ENV_SETTINGS \
54 "upgrade=if mmc rescan && " \
55 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
56 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
57 "\"Fail to upgrade.\n" \
58 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
59 "; fi\0" \
60 "core_mask=0xF\0" \
61 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
62setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
63setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
64setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
65 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
66setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
67setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
68setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
69 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
70setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
71setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
72setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
73 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
74setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
75setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
76setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
77 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
78setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
79setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
80setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
81 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
82 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
83setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
84setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
85setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
86setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
87 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
88 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
89setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
90setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
91setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
92setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
93setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
94 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
95 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
96setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
97setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
98setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
99setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
100setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
101setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
102
103/*
104 * Environment configuration
105 */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]106
107/* Cli configuration */
108#define CONFIG_SYS_CBSIZE SZ_2K
109
110/*
111 * Callback configuration
112 */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]113
114#endif /* _CONFIG_HSDK_H_ */