blob: 48a2c0bf213d9bb33d73438a85e7f1bd7faa3d40 [file] [log] [blame]
wdenk6f213472003-08-29 22:00:43 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/*
29 * CPU specific code
30 */
31
32#include <common.h>
33#include <command.h>
34#include <arm926ejs.h>
35
Wolfgang Denkd87080b2006-03-31 18:32:53 +020036#ifdef CONFIG_USE_IRQ
37DECLARE_GLOBAL_DATA_PTR;
38#endif
39
wdenk6f213472003-08-29 22:00:43 +000040/* read co-processor 15, register #1 (control register) */
41static unsigned long read_p15_c1 (void)
42{
43 unsigned long value;
44
45 __asm__ __volatile__(
46 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
47 : "=r" (value)
48 :
49 : "memory");
50
51#ifdef MMU_DEBUG
52 printf ("p15/c1 is = %08lx\n", value);
53#endif
54 return value;
55}
56
57/* write to co-processor 15, register #1 (control register) */
58static void write_p15_c1 (unsigned long value)
59{
60#ifdef MMU_DEBUG
61 printf ("write %08lx to p15/c1\n", value);
62#endif
63 __asm__ __volatile__(
64 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
65 :
66 : "r" (value)
67 : "memory");
68
69 read_p15_c1 ();
70}
71
72static void cp_delay (void)
73{
74 volatile int i;
75
Wolfgang Denk74f43042005-09-25 01:48:28 +020076 /* copro seems to need some delay between reading and writing */
wdenk6f213472003-08-29 22:00:43 +000077 for (i = 0; i < 100; i++);
78}
79
Wolfgang Denk74f43042005-09-25 01:48:28 +020080/* See also ARM926EJ-S Technical Reference Manual */
wdenk6f213472003-08-29 22:00:43 +000081#define C1_MMU (1<<0) /* mmu off/on */
82#define C1_ALIGN (1<<1) /* alignment faults off/on */
83#define C1_DC (1<<2) /* dcache off/on */
Wolfgang Denk74f43042005-09-25 01:48:28 +020084
85#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
wdenk6f213472003-08-29 22:00:43 +000086#define C1_SYS_PROT (1<<8) /* system protection */
87#define C1_ROM_PROT (1<<9) /* ROM protection */
88#define C1_IC (1<<12) /* icache off/on */
Wolfgang Denk74f43042005-09-25 01:48:28 +020089#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
90
wdenk6f213472003-08-29 22:00:43 +000091
92int cpu_init (void)
93{
94 /*
wdenka8c7c702003-12-06 19:49:23 +000095 * setup up stacks if necessary
wdenk6f213472003-08-29 22:00:43 +000096 */
97#ifdef CONFIG_USE_IRQ
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
wdenka8c7c702003-12-06 19:49:23 +000099 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
100#endif
101 return 0;
wdenk6f213472003-08-29 22:00:43 +0000102}
103
104int cleanup_before_linux (void)
105{
106 /*
107 * this function is called just before we call linux
108 * it prepares the processor for linux
109 *
110 * we turn off caches etc ...
111 */
112
113 unsigned long i;
114
115 disable_interrupts ();
116
117 /* turn off I/D-cache */
118 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
119 i &= ~(C1_DC | C1_IC);
120 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
121
122 /* flush I/D-cache */
123 i = 0;
124 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
Wolfgang Denk74f43042005-09-25 01:48:28 +0200125
wdenk6f213472003-08-29 22:00:43 +0000126 return (0);
127}
128
129int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
130{
wdenk6f213472003-08-29 22:00:43 +0000131 disable_interrupts ();
132 reset_cpu (0);
133 /*NOTREACHED*/
134 return (0);
135}
136
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400137/* cache_bit must be either C1_IC or C1_DC */
138static void cache_enable(uint32_t cache_bit)
wdenk6f213472003-08-29 22:00:43 +0000139{
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400140 uint32_t reg;
wdenk6f213472003-08-29 22:00:43 +0000141
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400142 reg = read_p15_c1(); /* get control reg. */
143 cp_delay();
144 write_p15_c1(reg | cache_bit);
wdenk6f213472003-08-29 22:00:43 +0000145}
146
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400147/* cache_bit must be either C1_IC or C1_DC */
148static void cache_disable(uint32_t cache_bit)
wdenk6f213472003-08-29 22:00:43 +0000149{
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400150 uint32_t reg;
wdenk6f213472003-08-29 22:00:43 +0000151
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400152 reg = read_p15_c1();
153 cp_delay();
154 write_p15_c1(reg & ~cache_bit);
wdenk6f213472003-08-29 22:00:43 +0000155}
156
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400157void icache_enable(void)
wdenk6f213472003-08-29 22:00:43 +0000158{
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400159 cache_enable(C1_IC);
160}
161
162void icache_disable(void)
163{
164 cache_disable(C1_IC);
165}
166
167int icache_status(void)
168{
169 return (read_p15_c1() & C1_IC) != 0;
170}
171
172void dcache_enable(void)
173{
174 cache_enable(C1_DC);
175}
176
177void dcache_disable(void)
178{
179 cache_disable(C1_DC);
180}
181
182int dcache_status(void)
183{
184 return (read_p15_c1() & C1_DC) != 0;
wdenk6f213472003-08-29 22:00:43 +0000185}