blob: 84998d4392a6cf4441036127088a0e704e7c0c05 [file] [log] [blame]
stefano babic5e5803e2007-08-30 23:01:49 +02001/*
2 * (C) Copyright 2007
3 * Stefano Babic, DENX Gmbh, sbabic@denx.de
4 *
5 * (C) Copyright 2004
6 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
7 *
8 * (C) Copyright 2002
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * Configuation settings for the LUBBOCK board.
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
44
45#define LITTLEENDIAN 1 /* used by usb_ohci.c */
46
47#define CONFIG_MMC 1
48#define BOARD_LATE_INIT 1
49
50#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
51
52#define RTC
53
54/*
55 * Size of malloc() pool
56 */
57#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
58#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
59
60/*
61 * Hardware drivers
62 */
63
64/*
65 * select serial console configuration
66 */
67#define CONFIG_SERIAL_MULTI
68#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
69#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
70#define CONFIG_STUART 1 /* we use STUART on Conxs */
71
72/* allow to overwrite serial and ethaddr */
73#define CONFIG_ENV_OVERWRITE
74
75#define CONFIG_BAUDRATE 38400
76
77#define CONFIG_DOS_PARTITION 1
78
79/*
80 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_MMC
85#define CONFIG_CMD_FAT
86#define CONFIG_CMD_IMLS
87#define CONFIG_CMD_PING
88#define CONFIG_CMD_USB
89
90/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91
92#undef CONFIG_SHOW_BOOT_PROGRESS
93
94#define CONFIG_BOOTDELAY 3
95#define CONFIG_SERVERIP 192.168.1.99
96#define CONFIG_BOOTCOMMAND "run boot_flash"
97#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
98 " rw root=/dev/ram initrd=0xa0800000,5m"
99
100#define CONFIG_EXTRA_ENV_SETTINGS \
101 "program_boot_mmc=" \
102 "mw.b 0xa0010000 0xff 0x20000; " \
103 "if mmcinit && " \
104 "fatload mmc 0 0xa0010000 u-boot.bin; " \
105 "then " \
106 "protect off 0x0 0x1ffff; " \
107 "erase 0x0 0x1ffff; " \
108 "cp.b 0xa0010000 0x0 0x20000; " \
109 "fi\0" \
110 "program_uzImage_mmc=" \
111 "mw.b 0xa0010000 0xff 0x180000; " \
112 "if mmcinit && " \
113 "fatload mmc 0 0xa0010000 uzImage; " \
114 "then " \
115 "protect off 0x40000 0x1bffff; " \
116 "erase 0x40000 0x1bffff; " \
117 "cp.b 0xa0010000 0x40000 0x180000; " \
118 "fi\0" \
119 "program_ramdisk_mmc=" \
120 "mw.b 0xa0010000 0xff 0x500000; " \
121 "if mmcinit && " \
122 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
123 "then " \
124 "protect off 0x1c0000 0x6bffff; " \
125 "erase 0x1c0000 0x6bffff; " \
126 "cp.b 0xa0010000 0x1c0000 0x500000; " \
127 "fi\0" \
128 "boot_mmc=" \
129 "if mmcinit && " \
130 "fatload mmc 0 0xa0030000 uzImage && " \
131 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
132 "then " \
133 "bootm 0xa0030000; " \
134 "fi\0" \
135 "boot_flash=" \
136 "cp.b 0x1c0000 0xa0800000 0x500000; " \
137 "bootm 0x40000\0" \
138
139#define CONFIG_SETUP_MEMORY_TAGS 1
140#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
141/* #define CONFIG_INITRD_TAG 1 */
142
143#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
144#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
145#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
146#endif
147
148/*
149 * Miscellaneous configurable options
150 */
151#define CFG_HUSH_PARSER 1
152#define CFG_PROMPT_HUSH_PS2 "> "
153
154#define CFG_LONGHELP /* undef to save memory */
155#ifdef CFG_HUSH_PARSER
156#define CFG_PROMPT "$ " /* Monitor Command Prompt */
157#else
158#define CFG_PROMPT "=> " /* Monitor Command Prompt */
159#endif
160#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
161#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
162#define CFG_MAXARGS 16 /* max number of command args */
163#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
164#define CFG_DEVICE_NULLDEV 1
165
166#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
167#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
168
169#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
170
171#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
172
173#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
174#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
175
176 /* valid baudrates */
177#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
178
179#define CFG_MMC_BASE 0xF0000000
180
181/*
182 * Stack sizes
183 *
184 * The stack sizes are set up in start.S using the settings below
185 */
186#define CONFIG_STACKSIZE (128*1024) /* regular stack */
187#ifdef CONFIG_USE_IRQ
188#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
189#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
190#endif
191
192/*
193 * Physical Memory Map
194 */
195#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
196#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
197#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
198#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
199#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
200#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
201#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
202#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
203#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
204
205#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
206
207#define CFG_DRAM_BASE 0xa0000000
208#define CFG_DRAM_SIZE 0x04000000
209
210#define CFG_FLASH_BASE PHYS_FLASH_1
211
212/*
213 * GPIO settings
214 */
215#define CFG_GPSR0_VAL 0x00018000
216#define CFG_GPSR1_VAL 0x00000000
217#define CFG_GPSR2_VAL 0x400dc000
218#define CFG_GPSR3_VAL 0x00000000
219#define CFG_GPCR0_VAL 0x00000000
220#define CFG_GPCR1_VAL 0x00000000
221#define CFG_GPCR2_VAL 0x00000000
222#define CFG_GPCR3_VAL 0x00000000
223#define CFG_GPDR0_VAL 0x00018000
224#define CFG_GPDR1_VAL 0x00028801
225#define CFG_GPDR2_VAL 0x520dc000
226#define CFG_GPDR3_VAL 0x0001E000
227#define CFG_GAFR0_L_VAL 0x801c0000
228#define CFG_GAFR0_U_VAL 0x00000013
229#define CFG_GAFR1_L_VAL 0x6990100A
230#define CFG_GAFR1_U_VAL 0x00000008
231#define CFG_GAFR2_L_VAL 0xA0000000
232#define CFG_GAFR2_U_VAL 0x010900F2
233#define CFG_GAFR3_L_VAL 0x54000003
234#define CFG_GAFR3_U_VAL 0x00002401
235#define CFG_GRER0_VAL 0x00000000
236#define CFG_GRER1_VAL 0x00000000
237#define CFG_GRER2_VAL 0x00000000
238#define CFG_GRER3_VAL 0x00000000
239#define CFG_GFER0_VAL 0x00000000
240#define CFG_GFER1_VAL 0x00000000
241#define CFG_GFER2_VAL 0x00000000
242#define CFG_GFER3_VAL 0x00000020
243
244
245#define CFG_PSSR_VAL 0x20 /* CHECK */
246
247/*
248 * Clock settings
249 */
250#define CFG_CKEN 0x01FFFFFF /* CHECK */
251#define CFG_CCCR 0x02000290 /* 520Mhz */
252
253/*
254 * Memory settings
255 */
256
257#define CFG_MSC0_VAL 0x4df84df0
258#define CFG_MSC1_VAL 0x7ff87ff4
259#define CFG_MSC2_VAL 0xa26936d4
260#define CFG_MDCNFG_VAL 0x880009C9
261#define CFG_MDREFR_VAL 0x20ca201e
262#define CFG_MDMRS_VAL 0x00220022
263
264#define CFG_FLYCNFG_VAL 0x00000000
265#define CFG_SXCNFG_VAL 0x40044004
266
267/*
268 * PCMCIA and CF Interfaces
269 */
270#define CFG_MECR_VAL 0x00000001
271#define CFG_MCMEM0_VAL 0x00004204
272#define CFG_MCMEM1_VAL 0x00010204
273#define CFG_MCATT0_VAL 0x00010504
274#define CFG_MCATT1_VAL 0x00010504
275#define CFG_MCIO0_VAL 0x00008407
276#define CFG_MCIO1_VAL 0x0000c108
277
278#define CONFIG_DRIVER_DM9000 1
279#define CONFIG_DRIVER_DM9000 1
280#define CONFIG_DM9000_BASE 0x08000000
281#define DM9000_IO CONFIG_DM9000_BASE
282#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
283/* #define CONFIG_DM9000_USE_8BIT */
284/* #define CONFIG_DM9000_USE_16BIT */
285#define CONFIG_DM9000_USE_32BIT
286
287#define CONFIG_USB_OHCI_NEW 1
288#define CFG_USB_OHCI_BOARD_INIT 1
289#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
290#define CFG_USB_OHCI_REGS_BASE 0x4C000000
291#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
292#define CONFIG_USB_STORAGE 1
293#define CFG_USB_OHCI_CPU_INIT 1
294
295/*
296 * FLASH and environment organization
297 */
298
299#define CFG_FLASH_CFI
300#define CFG_FLASH_CFI_DRIVER 1
301
302#define CFG_MONITOR_BASE 0
303#define CFG_MONITOR_LEN 0x40000
304
305#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
306#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
307
308/* timeout values are in ticks */
309#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
310#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
311
312/* write flash less slowly */
313#define CFG_FLASH_USE_BUFFER_WRITE 1
314
315/* Flash environment locations */
316#define CFG_ENV_IS_IN_FLASH 1
317#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
318#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
319#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
320
321/* Address and size of Redundant Environment Sector */
322#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
323#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
324
325#endif /* __CONFIG_H */