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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ae8d3d236a3426dff4c1dfe1e8d61b54cd3a29af / . / arch / arm / mach-k3 / j7200 / clk-data.c
blob: 7e55e48b923df1df07f4fa6067c24c6fa8d42c36 [file] [log] [blame]
Dave Gerlach277729e2021-06-11 11:45:18 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * J7200 specific clock platform data
4 *
Dave Gerlachae8d3d22021-09-07 17:16:56 -0500[diff] [blame^]5 * This file is auto generated. Please do not hand edit and report any issues
6 * to Dave Gerlach <d-gerlach@ti.com>.
7 *
8 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
Dave Gerlach277729e2021-06-11 11:45:18 +0300[diff] [blame]9 */
Dave Gerlachae8d3d22021-09-07 17:16:56 -0500[diff] [blame^]10
Dave Gerlach277729e2021-06-11 11:45:18 +0300[diff] [blame]11#include "k3-clk.h"
12
13static const char * const gluelogic_hfosc0_clkout_parents[] = {
14 "osc_19_2_mhz",
15 "osc_20_mhz",
16 "osc_24_mhz",
17 "osc_25_mhz",
18 "osc_26_mhz",
19 "osc_27_mhz",
20};
21
22static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
23 "board_0_mcu_ospi0_dqs_out",
24 "fss_mcu_0_ospi_0_ospi_oclk_clk",
25};
26
27static const char * const wkup_fref_clksel_out0_parents[] = {
28 "gluelogic_hfosc0_clkout",
29 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
30};
31
32static const char * const main_pll_hfosc_sel_out1_parents[] = {
33 "gluelogic_hfosc0_clkout",
34 "board_0_hfosc1_clk_out",
35};
36
37static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
38 "wkup_fref_clksel_out0",
39 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
40};
41
42static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
43 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
44 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
45};
46
47static const char * const mcuusart_clk_sel_out0_parents[] = {
48 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
49 "postdiv2_16fft_main_1_hsdivout5_clk",
50};
51
52static const char * const wkup_gpio0_clksel_out0_parents[] = {
53 "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
54 "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
55 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
56 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
57};
58
59static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
60 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
61 "gluelogic_hfosc0_clkout",
62};
63
64static const char * const main_pll_hfosc_sel_out0_parents[] = {
65 "gluelogic_hfosc0_clkout",
66 "board_0_hfosc1_clk_out",
67};
68
69static const char * const main_pll_hfosc_sel_out12_parents[] = {
70 "gluelogic_hfosc0_clkout",
71 "board_0_hfosc1_clk_out",
72};
73
74static const char * const main_pll_hfosc_sel_out14_parents[] = {
75 "gluelogic_hfosc0_clkout",
76 "board_0_hfosc1_clk_out",
77};
78
79static const char * const main_pll_hfosc_sel_out2_parents[] = {
80 "gluelogic_hfosc0_clkout",
81 "board_0_hfosc1_clk_out",
82};
83
84static const char * const main_pll_hfosc_sel_out3_parents[] = {
85 "gluelogic_hfosc0_clkout",
86 "board_0_hfosc1_clk_out",
87};
88
89static const char * const main_pll_hfosc_sel_out4_parents[] = {
90 "gluelogic_hfosc0_clkout",
91 "board_0_hfosc1_clk_out",
92};
93
94static const char * const main_pll_hfosc_sel_out7_parents[] = {
95 "gluelogic_hfosc0_clkout",
96 "board_0_hfosc1_clk_out",
97};
98
99static const char * const main_pll_hfosc_sel_out8_parents[] = {
100 "gluelogic_hfosc0_clkout",
101 "board_0_hfosc1_clk_out",
102};
103
104static const char * const usb0_refclk_sel_out0_parents[] = {
105 "gluelogic_hfosc0_clkout",
106 "board_0_hfosc1_clk_out",
107};
108
109static const char * const wkup_obsclk_mux_out0_parents[] = {
110 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
111 NULL,
112 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
113 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
114 "hsdiv4_16fft_mcu_1_hsdivout1_clk",
115 "hsdiv4_16fft_mcu_1_hsdivout2_clk",
116 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
117 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
118 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
119 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
120 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
121 "hsdiv4_16fft_mcu_2_hsdivout2_clk",
122 "hsdiv4_16fft_mcu_2_hsdivout3_clk",
123 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
124 "gluelogic_hfosc0_clkout",
125 "board_0_wkup_lf_clkin_out",
126};
127
128static const char * const main_pll4_xref_sel_out0_parents[] = {
129 "main_pll_hfosc_sel_out4",
130 "board_0_ext_refclk1_out",
131};
132
133static const char * const mcu_clkout_mux_out0_parents[] = {
134 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
135 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
136};
137
138static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
139 "main_pll_hfosc_sel_out0",
140 "hsdiv4_16fft_main_0_hsdivout0_clk",
141};
142
143static const char * const mcu_obsclk_outmux_out0_parents[] = {
144 "mcu_obsclk_div_out0",
145 "gluelogic_hfosc0_clkout",
146};
147
148static const char * const clkout_mux_out0_parents[] = {
149 "hsdiv4_16fft_main_3_hsdivout0_clk",
150 "hsdiv4_16fft_main_3_hsdivout0_clk",
151};
152
153static const char * const emmcsd_refclk_sel_out0_parents[] = {
154 "hsdiv4_16fft_main_0_hsdivout2_clk",
155 "hsdiv4_16fft_main_1_hsdivout2_clk",
156 "hsdiv4_16fft_main_3_hsdivout2_clk",
157 "hsdiv4_16fft_main_3_hsdivout2_clk",
158};
159
160static const char * const emmcsd_refclk_sel_out1_parents[] = {
161 "hsdiv4_16fft_main_0_hsdivout2_clk",
162 "hsdiv4_16fft_main_1_hsdivout2_clk",
163 "hsdiv4_16fft_main_3_hsdivout2_clk",
164 "hsdiv4_16fft_main_3_hsdivout2_clk",
165};
166
167static const char * const gtc_clk_mux_out0_parents[] = {
168 "hsdiv4_16fft_main_3_hsdivout1_clk",
169 "postdiv2_16fft_main_0_hsdivout6_clk",
170 "board_0_mcu_cpts0_rft_clk_out",
171 "board_0_cpts0_rft_clk_out",
172 "board_0_mcu_ext_refclk0_out",
173 "board_0_ext_refclk1_out",
174 NULL,
175 NULL,
176 NULL,
177 NULL,
178 NULL,
179 NULL,
180 NULL,
181 NULL,
182 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
183 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
184};
185
186static const char * const obsclk1_mux_out0_parents[] = {
187 NULL,
188 "hsdiv0_16fft_main_8_hsdivout0_clk",
189 NULL,
190 NULL,
191};
192
193static const char * const gpmc_fclk_sel_out0_parents[] = {
194 "hsdiv4_16fft_main_0_hsdivout3_clk",
195 "hsdiv4_16fft_main_2_hsdivout1_clk",
196 "hsdiv4_16fft_main_2_hsdivout1_clk",
197 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
198};
199
200static const char * const audio_refclko_mux_out0_parents[] = {
201 NULL,
202 NULL,
203 NULL,
204 NULL,
205 NULL,
206 NULL,
207 NULL,
208 NULL,
209 NULL,
210 NULL,
211 NULL,
212 NULL,
213 NULL,
214 NULL,
215 NULL,
216 NULL,
217 NULL,
218 NULL,
219 NULL,
220 NULL,
221 NULL,
222 NULL,
223 NULL,
224 NULL,
225 NULL,
226 NULL,
227 NULL,
228 NULL,
229 "hsdiv2_16fft_main_4_hsdivout2_clk",
230 NULL,
231 NULL,
232 NULL,
233};
234
235static const char * const audio_refclko_mux_out1_parents[] = {
236 NULL,
237 NULL,
238 NULL,
239 NULL,
240 NULL,
241 NULL,
242 NULL,
243 NULL,
244 NULL,
245 NULL,
246 NULL,
247 NULL,
248 NULL,
249 NULL,
250 NULL,
251 NULL,
252 NULL,
253 NULL,
254 NULL,
255 NULL,
256 NULL,
257 NULL,
258 NULL,
259 NULL,
260 NULL,
261 NULL,
262 NULL,
263 NULL,
264 "hsdiv2_16fft_main_4_hsdivout2_clk",
265 NULL,
266 NULL,
267 NULL,
268};
269
270static const char * const obsclk0_mux_out0_parents[] = {
271 "hsdiv4_16fft_main_0_hsdivout0_clk",
272 "hsdiv4_16fft_main_1_hsdivout0_clk",
273 "hsdiv4_16fft_main_2_hsdivout0_clk",
274 "hsdiv4_16fft_main_3_hsdivout0_clk",
275 "hsdiv2_16fft_main_4_hsdivout0_clk",
276 NULL,
277 NULL,
278 NULL,
279 NULL,
280 NULL,
281 NULL,
282 NULL,
283 "hsdiv0_16fft_main_12_hsdivout0_clk",
284 "obsclk1_mux_out0",
285 "hsdiv1_16fft_main_14_hsdivout0_clk",
286 NULL,
287 NULL,
288 NULL,
289 NULL,
290 NULL,
291 NULL,
292 NULL,
293 NULL,
294 NULL,
295 NULL,
296 NULL,
297 NULL,
298 "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
299 "board_0_wkup_lf_clkin_out",
300 "hsdiv4_16fft_main_0_hsdivout0_clk",
301 "board_0_hfosc1_clk_out",
302 "gluelogic_hfosc0_clkout",
303};
304
305static const struct clk_data clk_list[] = {
306 CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
307 CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
308 CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
309 CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
310 CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
311 CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
312 CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
313 CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
314 CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
315 CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
316 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
317 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
318 CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
319 CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
320 CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0),
321 CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
322 CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
323 CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
324 CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
325 CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
Suman Anna326c03b2021-09-07 17:16:55 -0500[diff] [blame]326 CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0),
327 CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0),
Dave Gerlach277729e2021-06-11 11:45:18 +0300[diff] [blame]328 CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
329 CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
330 CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
331 CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
332 CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
333 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
334 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
335 CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
336 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
337 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
338 CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
339 CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
340 CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
341 CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
342 CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
343 CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
344 CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
345 CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
346 CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
347 CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
348 CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
349 CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
350 CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
351 CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
352 CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
353 CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
354 CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
355 CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0),
356 CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0),
357 CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
358 CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
359 CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
360 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
361 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
362 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
363 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
364 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
365 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
366 CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
Suman Anna326c03b2021-09-07 17:16:55 -0500[diff] [blame]367 CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0),
368 CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0),
Dave Gerlach277729e2021-06-11 11:45:18 +0300[diff] [blame]369 CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
370 CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
371 CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
372 CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
373 CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
374 CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
375 CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
376 CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
377 CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
378 CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
379 CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
380 CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
381 CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
382 CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
383 CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
384 CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
385 CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
386 CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
387 CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
388 CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
389 CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
390 CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
391 CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
392 CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
393 CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
394 CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
395 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
396 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
397 CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
398 CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
399 CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
400 CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
401 CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
402 CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
403 CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
404 CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
405 CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
406 CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
407 CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
408 CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0),
409 CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0),
410 CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
411 CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
412 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
413 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
414};
415
416static const struct dev_clk soc_dev_clk_data[] = {
417 DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
418 DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
419 DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
420 DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
421 DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"),
422 DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
423 DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
424 DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
425 DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
426 DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
427 DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
428 DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
429 DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
430 DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
431 DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
432 DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
433 DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
434 DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
435 DEV_CLK(61, 1, "gtc_clk_mux_out0"),
436 DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
437 DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"),
438 DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
439 DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
440 DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
441 DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
442 DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
443 DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
444 DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
445 DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"),
446 DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"),
447 DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"),
448 DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
449 DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"),
450 DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
451 DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
452 DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"),
453 DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
454 DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
455 DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
456 DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
457 DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
458 DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
459 DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
460 DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
461 DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
462 DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
463 DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
464 DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
465 DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
466 DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"),
467 DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"),
468 DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"),
469 DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
470 DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
471 DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
472 DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
473 DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
474 DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"),
475 DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
476 DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
477 DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"),
478 DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
479 DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
480 DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
481 DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
482 DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
483 DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"),
484 DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
485 DEV_CLK(149, 2, "mcuusart_clk_sel_out0"),
486 DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
487 DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"),
488 DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
489 DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
490 DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
491 DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
492 DEV_CLK(157, 5, "osbclk0_div_out0"),
493 DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
494 DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"),
495 DEV_CLK(157, 15, "mcu_obsclk_div_out0"),
496 DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"),
497 DEV_CLK(157, 35, "clkout_mux_out0"),
498 DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"),
499 DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"),
500 DEV_CLK(157, 38, "osbclk0_div_out0"),
501 DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
502 DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
503 DEV_CLK(157, 69, "mcu_clkout_mux_out0"),
504 DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
505 DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
506 DEV_CLK(157, 77, "audio_refclko_mux_out1"),
507 DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"),
508 DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
509 DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
510 DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"),
511 DEV_CLK(157, 131, "audio_refclko_mux_out0"),
512 DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"),
513 DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"),
514 DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
515 DEV_CLK(157, 184, "gpmc_fclk_sel_out0"),
516 DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
517 DEV_CLK(157, 192, "osbclk0_div_out0"),
518 DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"),
519 DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"),
520 DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"),
521 DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"),
522 DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"),
523 DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"),
524 DEV_CLK(157, 206, "obsclk1_mux_out0"),
525 DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"),
526 DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
527 DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"),
528 DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"),
529 DEV_CLK(157, 223, "board_0_hfosc1_clk_out"),
530 DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"),
531 DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"),
532 DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"),
533 DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
534 DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
535 DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
536 DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
537 DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
538 DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
539 DEV_CLK(288, 12, "usb0_refclk_sel_out0"),
540 DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"),
541 DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
542 DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
543 DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
544};
545
546const struct ti_k3_clk_platdata j7200_clk_platdata = {
547 .clk_list = clk_list,
548 .clk_list_cnt = 108,
549 .soc_dev_clk_data = soc_dev_clk_data,
550 .soc_dev_clk_data_cnt = 127,
551};