Blame - arch/Kconfig.nxp - platform/external/u-boot

blob: 8c5a6f63a9a5873367791e5238cd5b61752cd2d6 [file] [log] [blame]

Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	1	config NXP_ESBC
				2	bool "NXP ESBC (secure boot) functionality"
				3	help
				4	Enable Freescale Secure Boot feature. Normally selected by defconfig.
				5	If unsure, do not change.
				6
				7	menu "Chain of trust / secure boot options"
Udit Agarwal	5536c3c	2019-11-07 16:11:32 +0000	[diff] [blame]	8	depends on !FIT_SIGNATURE && NXP_ESBC
Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	9
				10	config CHAIN_OF_TRUST
Tom Rini	2852267	2017-03-01 16:51:58 -0500	[diff] [blame]	11	select FSL_CAAM
Gaurav Jain	66e5471	2022-06-09 16:32:15 +0530	[diff] [blame]	12	select ARCH_MISC_INIT
Tom Rini	c9f8518	2022-06-16 14:04:39 -0400	[diff] [blame]	13	select FSL_SEC_MON
Ley Foon Tan	0680f1b	2017-05-03 17:13:32 +0800	[diff] [blame]	14	select SPL_BOARD_INIT if (ARM && SPL)
Alexandru Gagniuc	0721209	2021-09-02 19:54:19 -0500	[diff] [blame]	15	select SPL_HASH if (ARM && SPL)
Tom Rini	089df18	2017-05-15 12:17:49 -0400	[diff] [blame]	16	select SHA_HW_ACCEL
				17	select SHA_PROG_HW_ACCEL
Simon Glass	2be2965	2017-07-23 21:19:39 -0600	[diff] [blame]	18	select ENV_IS_NOWHERE
Tom Rini	f6c1f91	2022-06-25 11:02:45 -0400	[diff] [blame]	19	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
Sumit Garg	86c773f	2018-01-09 01:27:46 +0530	[diff] [blame]	20	select CMD_EXT4 if ARM
				21	select CMD_EXT4_WRITE if ARM
Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	22	imply CMD_BLOB
				23	imply CMD_HASH if ARM
				24	def_bool y
Simon Glass	ea7971f	2017-05-17 03:25:16 -0600	[diff] [blame]	25
				26	config CMD_ESBC_VALIDATE
				27	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
Tom Rini	9314533	2022-06-16 14:04:35 -0400	[diff] [blame]	28	default y
Simon Glass	ea7971f	2017-05-17 03:25:16 -0600	[diff] [blame]	29	help
				30	This option enables two commands used for secure booting:
				31
				32	esbc_validate - validate signature using RSA verification
				33	esbc_halt - put the core in spin loop (Secure Boot Only)
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	34
Tom Rini	2b2817b	2022-06-16 14:04:37 -0400	[diff] [blame]	35	config ESBC_HDR_LS
				36	bool
				37
				38	config ESBC_ADDR_64BIT
				39	def_bool y
				40	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
				41	help
				42	For Layerscape based platforms, ESBC image Address in Header is 64bit.
				43
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	44	config SYS_FSL_SFP_BE
				45	def_bool y
Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	46	depends on PPC \|\| FSL_LSCH2 \|\| ARCH_LS1021A
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	47
				48	config SYS_FSL_SFP_LE
				49	def_bool y
Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	50	depends on !SYS_FSL_SFP_BE
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	51
				52	choice
				53	prompt "SFP IP revision"
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	54	default SYS_FSL_SFP_VER_3_0 if PPC
				55	default SYS_FSL_SFP_VER_3_4
				56
				57	config SYS_FSL_SFP_VER_3_0
				58	bool "SFP version 3.0"
				59
				60	config SYS_FSL_SFP_VER_3_2
				61	bool "SFP version 3.2"
				62
				63	config SYS_FSL_SFP_VER_3_4
				64	bool "SFP version 3.4"
				65
				66	endchoice
				67
Tom Rini	5aad0a1	2022-06-17 16:24:32 -0400	[diff] [blame]	68	config SPL_UBOOT_KEY_HASH
				69	string "Non-SRK key hash for U-Boot public/private key pair"
				70	depends on SPL
				71	default ""
				72	help
				73	Set the key hash for U-Boot here if public/private key pair used to
				74	sign U-boot are different from the SRK hash put in the fuse. Example
				75	of a key hash is
				76	41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
				77	Otherwise leave this empty.
				78
Tom Rini	f4cd75e	2022-06-17 16:24:34 -0400	[diff] [blame]	79	if PPC
				80
				81	config BOOTSCRIPT_COPY_RAM
				82	bool "Secure boot copies boot script to RAM"
				83	help
				84	On systems that support chain of trust booting, a number of addresses
				85	are required to set variables that are used in the copying and then
				86	verification of different parts of the system. If enabled, the subsequent
				87	options are for what location to use in each step.
				88
				89	config BS_ADDR_DEVICE
				90	hex "Address in RAM for bs_device"
				91	depends on BOOTSCRIPT_COPY_RAM
				92
				93	config BS_SIZE
				94	hex "The size of bs_size which is the amount read from bs_device"
				95	depends on BOOTSCRIPT_COPY_RAM
				96
				97	config BS_ADDR_RAM
				98	hex "Address in RAM for bs_ram"
				99	depends on BOOTSCRIPT_COPY_RAM
				100
				101	config BS_HDR_ADDR_DEVICE
				102	hex "Address in RAM for bs_hdr_device"
				103	depends on BOOTSCRIPT_COPY_RAM
				104
				105	config BS_HDR_SIZE
				106	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
				107	depends on BOOTSCRIPT_COPY_RAM
				108
				109	config BS_HDR_ADDR_RAM
				110	hex "Address in RAM for bs_hdr_ram"
				111	depends on BOOTSCRIPT_COPY_RAM
				112
				113	config BOOTSCRIPT_HDR_ADDR
				114	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
				115	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
				116
				117	endif
				118
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	119	config SYS_FSL_SRK_LE
				120	def_bool y
Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	121	depends on ARM
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	122
				123	config KEY_REVOCATION
				124	def_bool y
Tom Rini	540b73a	2022-06-17 16:24:31 -0400	[diff] [blame]	125
				126	endmenu
				127
				128	comment "Other functionality shared between NXP SoCs"
Tom Rini	601483f	2022-06-16 14:04:40 -0400	[diff] [blame]	129
Tom Rini	28f9c31	2022-03-24 17:17:58 -0400	[diff] [blame]	130	config DEEP_SLEEP
				131	bool "Enable SoC deep sleep feature"
Tom Rini	9314533	2022-06-16 14:04:35 -0400	[diff] [blame]	132	depends on ARCH_T1024 \|\| ARCH_T1040 \|\| ARCH_T1042 \|\| ARCH_LS1021A
				133	default y
Tom Rini	28f9c31	2022-03-24 17:17:58 -0400	[diff] [blame]	134	help
				135	Indicates this SoC supports deep sleep feature. If deep sleep is
				136	supported, core will start to execute uboot when wakes up.
				137
Tom Rini	a552ffc	2022-06-20 08:07:44 -0400	[diff] [blame]	138	config LAYERSCAPE_NS_ACCESS
				139	bool "Layerscape non-secure access support"
				140	depends on ARCH_LS1021A \|\| FSL_LSCH2
				141
Tom Rini	3dc2987	2022-06-20 08:07:45 -0400	[diff] [blame]	142	config PCIE1
				143	bool "PCIe controller #1"
				144	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
				145
				146	config PCIE2
				147	bool "PCIe controller #2"
				148	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
				149
				150	config PCIE3
				151	bool "PCIe controller #3"
				152	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
				153
				154	config PCIE4
				155	bool "PCIe controller #4"
				156	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
				157
Stephen Carlson	15347d2	2021-06-22 16:35:20 -0700	[diff] [blame]	158	config FSL_USE_PCA9547_MUX
				159	bool "Enable PCA9547 I2C Mux on Freescale boards"
Tom Rini	9314533	2022-06-16 14:04:35 -0400	[diff] [blame]	160	depends on PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3
Stephen Carlson	15347d2	2021-06-22 16:35:20 -0700	[diff] [blame]	161	help
				162	This option enables the PCA9547 I2C mux on Freescale boards.
				163
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	164	config VID
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	165	bool "Enable Freescale VID"
Tom Rini	9314533	2022-06-16 14:04:35 -0400	[diff] [blame]	166	depends on (PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3) && (I2C \|\| DM_I2C)
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	167	help
				168	This option enables setting core voltage based on individual
				169	values saved in SoC fuses.
				170
Tom Rini	d06e4b7	2021-12-12 22:12:31 -0500	[diff] [blame]	171	config SPL_VID
				172	bool "Enable Freescale VID in SPL"
Tom Rini	9314533	2022-06-16 14:04:35 -0400	[diff] [blame]	173	depends on (PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3) && (SPL_I2C \|\| DM_SPL_I2C)
Tom Rini	d06e4b7	2021-12-12 22:12:31 -0500	[diff] [blame]	174	help
				175	This option enables setting core voltage based on individual
				176	values saved in SoC fuses, in SPL.
				177
				178	if VID \|\| SPL_VID
				179
				180	config VID_FLS_ENV
				181	string "Environment variable for overriding VDD"
				182	help
				183	This option allows for specifying the environment variable
				184	to check to override VDD information.
				185
				186	config VOL_MONITOR_INA220
				187	bool "Enable the INA220 voltage monitor read"
				188	help
				189	This option enables INA220 voltage monitor read
				190	functionality. It is used by the common VID driver.
				191
				192	config VOL_MONITOR_IR36021_READ
				193	bool "Enable the IR36021 voltage monitor read"
				194	help
				195	This option enables IR36021 voltage monitor read
				196	functionality. It is used by the common VID driver.
				197
				198	config VOL_MONITOR_IR36021_SET
				199	bool "Enable the IR36021 voltage monitor set"
				200	help
				201	This option enables IR36021 voltage monitor set
				202	functionality. It is used by the common VID driver.
				203
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	204	config VOL_MONITOR_LTC3882_READ
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	205	bool "Enable the LTC3882 voltage monitor read"
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	206	help
				207	This option enables LTC3882 voltage monitor read
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	208	functionality. It is used by the common VID driver.
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	209
				210	config VOL_MONITOR_LTC3882_SET
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	211	bool "Enable the LTC3882 voltage monitor set"
Rajesh Bhagat	6f2d0a5	2018-01-17 16:13:04 +0530	[diff] [blame]	212	help
				213	This option enables LTC3882 voltage monitor set
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	214	functionality. It is used by the common VID driver.
				215
				216	config VOL_MONITOR_ISL68233_READ
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	217	bool "Enable the ISL68233 voltage monitor read"
				218	help
				219	This option enables ISL68233 voltage monitor read
				220	functionality. It is used by the common VID driver.
				221
				222	config VOL_MONITOR_ISL68233_SET
Stephen Carlson	b5ee48c	2021-02-08 11:11:29 +0100	[diff] [blame]	223	bool "Enable the ISL68233 voltage monitor set"
				224	help
				225	This option enables ISL68233 voltage monitor set
				226	functionality. It is used by the common VID driver.
Tom Rini	d06e4b7	2021-12-12 22:12:31 -0500	[diff] [blame]	227
				228	endif
Tom Rini	d43cd48	2022-03-30 18:07:32 -0400	[diff] [blame]	229
Tom Rini	1de46d9	2022-07-31 21:08:27 -0400	[diff] [blame]	230	config SYS_FSL_NUM_CC_PLLS
				231	int "Number of clock control PLLs"
				232	depends on MPC85xx \|\| FSL_LSCH2 \|\| FSL_LSCH3 \|\| ARCH_LS1021A \|\| ARCH_LS1028A
				233	default 2 if ARCH_LS1021A \|\| ARCH_LS1028A \|\| FSL_LSCH2
				234	default 6 if FSL_LSCH3 \|\| MPC85xx
				235
Tom Rini	923a855	2022-07-23 13:05:09 -0400	[diff] [blame]	236	config SYS_FSL_ESDHC_BE
				237	bool
				238
				239	config SYS_FSL_IFC_BE
				240	bool
				241
Tom Rini	d43cd48	2022-03-30 18:07:32 -0400	[diff] [blame]	242	config FSL_QIXIS
				243	bool "Enable QIXIS support"
Tom Rini	9314533	2022-06-16 14:04:35 -0400	[diff] [blame]	244	depends on PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3
Tom Rini	d43cd48	2022-03-30 18:07:32 -0400	[diff] [blame]	245
				246	config QIXIS_I2C_ACCESS
				247	bool "Access to QIXIS is over i2c"
				248	depends on FSL_QIXIS
				249	default y
Tom Rini	5cc1d92	2022-06-08 08:24:28 -0400	[diff] [blame]	250
				251	config HAS_FSL_DR_USB
				252	def_bool y
				253	depends on USB_EHCI_HCD && PPC