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Stefan Roese211ea912007-10-22 07:34:34 +02001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese211ea912007-10-22 07:34:34 +02006 */
7
8/*
9 * ehnus: change pll frequency.
10 * Wed Sep 5 11:45:17 CST 2007
11 * hsun@udtech.com.cn
12 */
13
14
15#include <common.h>
16#include <config.h>
17#include <command.h>
18#include <i2c.h>
19
20#ifdef CONFIG_CMD_EEPROM
21
22#define EEPROM_CONF_OFFSET 0
23#define EEPROM_TEST_OFFSET 16
24#define EEPROM_SDSTP_PARAM 16
25
26#define PLL_NAME_MAX 12
27#define BUF_STEP 8
28
29/* eeprom_wirtes 8Byte per op. */
30#define EEPROM_ALTER_FREQ(freq) \
31 do { \
32 int __i; \
33 for (__i = 0; __i < 2; __i++) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
Stefan Roese211ea912007-10-22 07:34:34 +020035 EEPROM_CONF_OFFSET + __i*BUF_STEP, \
36 pll_select[freq], \
37 BUF_STEP + __i*BUF_STEP); \
38 } while (0)
39
40#define PDEBUG
41#ifdef PDEBUG
42#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
43#else
44#define PLL_DEBUG
45#endif
46
47typedef enum {
48 PLL_ebc20,
49 PLL_333,
50 PLL_4001,
51 PLL_4002,
52 PLL_533,
53 PLL_600,
54 PLL_666, /* For now, kilauea can't support */
55 RCONF,
56 WTEST,
57 PLL_TOTAL
58} pll_freq_t;
59
60static const char
61pll_name[][PLL_NAME_MAX] = {
62 "PLL_ebc20",
63 "PLL_333",
64 "PLL_400@1",
65 "PLL_400@2",
66 "PLL_533",
67 "PLL_600",
68 "PLL_666",
69 "RCONF",
70 "WTEST",
71 ""
72};
73
74/*
75 * ehnus:
76 */
77static uchar
78pll_select[][EEPROM_SDSTP_PARAM] = {
79 /* 0: CPU 333MHz EBC 20MHz, for test only */
80 {
81 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
82 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
83 },
84
85 /* 0: 333 */
86 {
87 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
88 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
89 },
90
91 /* 1: 400_266 */
92 {
93 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
94 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
95 },
96
97 /* 2: 400 */
98 {
99 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
100 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
101 },
102
103 /* 3: 533 */
104 {
105 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
106 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
107 },
108
109 /* 4: 600 */
110 {
111 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
112 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
113 },
114
115 /* 5: 666 */
116 {
117 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
118 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
119 },
120
121 {}
122};
123
124static uchar
125testbuf[EEPROM_SDSTP_PARAM] = {
126 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
127 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
128};
129
130static void
131pll_debug(int off)
132{
133 int i;
134 uchar buffer[EEPROM_SDSTP_PARAM];
135
136 memset(buffer, 0, sizeof(buffer));
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
Stefan Roese211ea912007-10-22 07:34:34 +0200138 buffer, EEPROM_SDSTP_PARAM);
139
140 printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
141 for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
142 printf("%02x ", buffer[i]);
143 printf("\n");
144}
145
146static void
147test_write(void)
148{
149 printf("Debug: test eeprom_write ... ");
150
151 /*
152 * Write twice, 8 bytes per write
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
Stefan Roese211ea912007-10-22 07:34:34 +0200155 testbuf, 8);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
Stefan Roese211ea912007-10-22 07:34:34 +0200157 testbuf, 16);
158 printf("done\n");
159
160 pll_debug(EEPROM_TEST_OFFSET);
161}
162
163int
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200164do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Stefan Roese211ea912007-10-22 07:34:34 +0200165{
166 char c = '\0';
167 pll_freq_t pll_freq;
Stefan Roese211ea912007-10-22 07:34:34 +0200168
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200169 if (argc < 2)
170 return cmd_usage(cmdtp);
171
172 for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
Stefan Roese211ea912007-10-22 07:34:34 +0200173 if (!strcmp(pll_name[pll_freq], argv[1]))
174 break;
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200175 }
Stefan Roese211ea912007-10-22 07:34:34 +0200176
177 switch (pll_freq) {
178 case PLL_ebc20:
179 case PLL_333:
180 case PLL_4001:
181 case PLL_4002:
182 case PLL_533:
183 case PLL_600:
184 EEPROM_ALTER_FREQ(pll_freq);
185 break;
186
187 case PLL_666: /* not support */
188 printf("Choose this option will result in a boot failure."
189 "\nContinue? (Y/N): ");
190
191 c = getc(); putc('\n');
192
193 if ((c == 'y') || (c == 'Y')) {
194 EEPROM_ALTER_FREQ(pll_freq);
195 break;
196 }
197 goto ret;
198
199 case RCONF:
200 pll_debug(EEPROM_CONF_OFFSET);
201 goto ret;
202 case WTEST:
203 printf("DEBUG: write test\n");
204 test_write();
205 goto ret;
206
207 default:
Peter Tyser62c3ae72009-01-27 18:03:10 -0600208 printf("Invalid options\n\n");
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200209 return cmd_usage(cmdtp);
Stefan Roese211ea912007-10-22 07:34:34 +0200210 }
211
212 printf("PLL set to %s, "
213 "reset the board to take effect\n", pll_name[pll_freq]);
214
215 PLL_DEBUG;
216ret:
217 return 0;
218}
219
220U_BOOT_CMD(
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
Peter Tyser2fb26042009-01-27 18:03:12 -0600222 "change pll frequence",
Stefan Roese211ea912007-10-22 07:34:34 +0200223 "pllalter <selection> - change pll frequence \n\n\
224 ** New freq take effect after reset. ** \n\
225 ----------------------------------------------\n\
226 PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
227 \t Same as PLL_333 \n\
228 \t except \n\
229 \t EBC: 20 MHz \n\
230 ----------------------------------------------\n\
231 PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
232 \t VCO: 666 MHz \n\
233 \t CPU: 333 MHz \n\
234 \t PLB: 166 MHz \n\
235 \t OPB: 83 MHz \n\
236 \t DDR: 83 MHz \n\
237 ------------------------------------------------\n\
238 PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
239 \t VCO: 800 MHz \n\
240 \t CPU: 400 MHz \n\
241 \t PLB: 133 MHz \n\
242 \t OPB: 66 MHz \n\
243 \t DDR: 133 MHz \n\
244 ------------------------------------------------\n\
245 PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
246 \t VCO: 800 MHz \n\
247 \t CPU: 400 MHz \n\
248 \t PLB: 200 MHz \n\
249 \t OPB: 100 MHz \n\
250 \t DDR: 200 MHz \n\
251 ----------------------------------------------\n\
252 PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
253 \t VCO: 1066 MHz \n\
254 \t CPU: 533 MHz \n\
255 \t PLB: 177 MHz \n\
256 \t OPB: 88 MHz \n\
257 \t DDR: 177 MHz \n\
258 ----------------------------------------------\n\
259 PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
260 \t VCO: 1200 MHz \n\
261 \t CPU: 600 MHz \n\
262 \t PLB: 200 MHz \n\
263 \t OPB: 100 MHz \n\
264 \t DDR: 200 MHz \n\
265 ----------------------------------------------\n\
266 PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
267 \t VCO: 1333 MHz \n\
268 \t CPU: 666 MHz \n\
269 \t PLB: 166 MHz \n\
270 \t OPB: 83 MHz \n\
271 \t DDR: 166 MHz \n\
272 -----------------------------------------------\n\
273 RCONF: Read current eeprom configuration. \n\
274 -----------------------------------------------\n\
275 WTEST: Test EEPROM write with predefined values\n\
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200276 -----------------------------------------------"
277);
Stefan Roese211ea912007-10-22 07:34:34 +0200278
Stefan Roesebe88b162008-01-17 07:50:17 +0100279#endif /* CONFIG_CMD_EEPROM */