wdenk | 6dd652f | 2003-06-19 23:40:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 6dd652f | 2003-06-19 23:40:20 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _HYMOD_H_ |
| 9 | #define _HYMOD_H_ |
| 10 | |
| 11 | #include <linux/config.h> |
| 12 | #ifdef CONFIG_8260 |
| 13 | #include <asm/iopin_8260.h> |
| 14 | #endif |
| 15 | |
| 16 | /* |
| 17 | * hymod configuration data - passed by boot code via the board information |
| 18 | * structure (only U-Boot has support for this at the moment) |
| 19 | * |
| 20 | * there are three types of data passed up from the boot monitor. the first |
| 21 | * (type hymod_eeprom_t) is the eeprom data that was read off both the main |
| 22 | * (or mother) board and the mezzanine board (if any). this data defines how |
| 23 | * many Xilinx fpgas are on each board, and their types (among other things). |
| 24 | * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where |
| 25 | * in the physical address space the various Xilinx fpga access regions have |
| 26 | * been mapped by the boot rom. the third type of data (type xlx_iopins_t, |
| 27 | * one per Xilinx fpga) defines which io port pins are connected to the various |
| 28 | * signals required to program a Xilinx fpga. |
| 29 | * |
| 30 | * A ram/flash "bank" refers to memory controlled by the same chip select. |
| 31 | * |
| 32 | * the eeprom contents are defined as in technical note #2 - basically, |
| 33 | * a header, zero or more records in no particular order, and a 32 bit crc |
| 34 | * a record is 1 or more type bytes, a length byte and "length" bytes. |
| 35 | */ |
| 36 | |
| 37 | #define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ |
| 38 | #define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ |
| 39 | #define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ |
| 40 | |
| 41 | /* eeprom header */ |
| 42 | typedef |
| 43 | struct { |
| 44 | unsigned char id; /* eeprom id byte */ |
| 45 | unsigned char :1; |
| 46 | unsigned char ver:7; /* eeprom contents version number */ |
| 47 | unsigned long len; /* total # of bytes btw hdr and crc */ |
| 48 | } |
| 49 | hymod_eehdr_t; |
| 50 | |
| 51 | /* maximum number of bytes available for eeprom data records */ |
| 52 | #define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ |
| 53 | - sizeof (hymod_eehdr_t) \ |
| 54 | - sizeof (unsigned long)) |
| 55 | |
| 56 | /* eeprom data record */ |
| 57 | typedef |
| 58 | union { |
| 59 | struct { |
| 60 | unsigned char topbit:1; |
| 61 | unsigned char type:7; |
| 62 | unsigned char len; |
| 63 | unsigned char data[1]; /* variable length */ |
| 64 | } small; |
| 65 | struct { |
| 66 | unsigned short topbit:1; |
| 67 | unsigned short nxtbit:1; |
| 68 | unsigned short type:14; |
| 69 | unsigned short len; |
| 70 | unsigned char data[1]; /* variable length */ |
| 71 | } medium; |
| 72 | struct { |
| 73 | unsigned long topbit:1; |
| 74 | unsigned long nxtbit:1; |
| 75 | unsigned long type:30; |
| 76 | unsigned long len; |
| 77 | unsigned char data[1]; /* variable length */ |
| 78 | } large; |
| 79 | } |
| 80 | hymod_eerec_t; |
| 81 | |
| 82 | #define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ |
| 83 | #define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ |
| 84 | |
| 85 | /* eeprom record types */ |
| 86 | #define HYMOD_EEREC_SERNO 1 /* serial number */ |
| 87 | #define HYMOD_EEREC_DATE 2 /* date */ |
| 88 | #define HYMOD_EEREC_BATCH 3 /* batch id */ |
| 89 | #define HYMOD_EEREC_TYPE 4 /* board type */ |
| 90 | #define HYMOD_EEREC_REV 5 /* revision number */ |
| 91 | #define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ |
| 92 | #define HYMOD_EEREC_FLASH 7 /* flash sizes */ |
| 93 | #define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ |
| 94 | #define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ |
| 95 | #define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ |
| 96 | #define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ |
| 97 | #define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ |
| 98 | #define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ |
| 99 | #define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ |
| 100 | #define HYMOD_EEREC_BUSSPD 15 /* bus speed */ |
| 101 | #define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ |
| 102 | #define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ |
| 103 | #define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ |
| 104 | #define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ |
| 105 | |
| 106 | /* some dimensions */ |
| 107 | #define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ |
| 108 | #define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ |
| 109 | #define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ |
| 110 | #define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ |
| 111 | #define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ |
| 112 | |
| 113 | #define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ |
| 114 | |
| 115 | /* board types */ |
| 116 | #define HYMOD_BDTYPE_NONE 0 /* information not present */ |
| 117 | #define HYMOD_BDTYPE_IO 1 /* I/O main board */ |
| 118 | #define HYMOD_BDTYPE_CLP 2 /* CLP main board */ |
| 119 | #define HYMOD_BDTYPE_DSP 3 /* DSP main board */ |
| 120 | #define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ |
| 121 | #define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ |
| 122 | #define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ |
| 123 | #define HYMOD_BDTYPE_MAX 7 /* first invalid value */ |
| 124 | |
| 125 | /* Xilinx fpga types */ |
| 126 | #define HYMOD_XTYP_NONE 0 /* information not present */ |
| 127 | #define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ |
| 128 | #define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ |
| 129 | #define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ |
| 130 | #define HYMOD_XTYP_MAX 4 /* first invalid value */ |
| 131 | |
| 132 | /* Xilinx fpga speeds */ |
| 133 | #define HYMOD_XSPD_NONE 0 /* information not present */ |
| 134 | #define HYMOD_XSPD_SIX 1 |
| 135 | #define HYMOD_XSPD_SEVEN 2 |
| 136 | #define HYMOD_XSPD_EIGHT 3 |
| 137 | #define HYMOD_XSPD_MAX 4 /* first invalid value */ |
| 138 | |
| 139 | /* Xilinx fpga temperatures */ |
| 140 | #define HYMOD_XTMP_NONE 0 /* information not present */ |
| 141 | #define HYMOD_XTMP_COM 1 |
| 142 | #define HYMOD_XTMP_IND 2 |
| 143 | #define HYMOD_XTMP_MAX 3 /* first invalid value */ |
| 144 | |
| 145 | /* Xilinx fpga grades */ |
| 146 | #define HYMOD_XTMP_NONE 0 /* information not present */ |
| 147 | #define HYMOD_XTMP_NORMAL 1 |
| 148 | #define HYMOD_XTMP_ENGSAMP 2 |
| 149 | #define HYMOD_XTMP_MAX 3 /* first invalid value */ |
| 150 | |
| 151 | /* CPU types */ |
| 152 | #define HYMOD_CPUTYPE_NONE 0 /* information not present */ |
| 153 | #define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ |
| 154 | #define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ |
| 155 | |
| 156 | /* CPU/BUS/CPM clock speeds */ |
| 157 | #define HYMOD_CLKSPD_NONE 0 /* information not present */ |
| 158 | #define HYMOD_CLKSPD_33MHZ 1 |
| 159 | #define HYMOD_CLKSPD_66MHZ 2 |
| 160 | #define HYMOD_CLKSPD_100MHZ 3 |
| 161 | #define HYMOD_CLKSPD_133MHZ 4 |
| 162 | #define HYMOD_CLKSPD_166MHZ 5 |
| 163 | #define HYMOD_CLKSPD_200MHZ 6 |
| 164 | #define HYMOD_CLKSPD_MAX 7 /* first invalid value */ |
| 165 | |
| 166 | /* high speed serial chip types */ |
| 167 | #define HYMOD_HSSTYPE_NONE 0 /* information not present */ |
| 168 | #define HYMOD_HSSTYPE_AMCC52064 1 |
| 169 | #define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ |
| 170 | |
| 171 | /* a date (yyyy-mm-dd) */ |
| 172 | typedef |
| 173 | struct { |
| 174 | unsigned short year; |
| 175 | unsigned char month; |
| 176 | unsigned char day; |
| 177 | } |
| 178 | hymod_date_t; |
| 179 | |
| 180 | /* describes a Xilinx fpga */ |
| 181 | typedef |
| 182 | struct { |
| 183 | unsigned char type; /* chip type */ |
| 184 | unsigned char speed; /* chip speed rating */ |
| 185 | unsigned char temp; /* chip temperature rating */ |
| 186 | unsigned char grade; /* chip grade */ |
| 187 | } |
| 188 | hymod_xlx_t; |
| 189 | |
| 190 | /* describes a Motorola embedded processor */ |
| 191 | typedef |
| 192 | struct { |
| 193 | unsigned char type; /* CPU type */ |
| 194 | unsigned char cpuspd; /* speed of the PowerPC core */ |
| 195 | unsigned char busspd; /* speed of the system and 60x bus */ |
| 196 | unsigned char cpmspd; /* speed of the CPM co-processor */ |
| 197 | } |
| 198 | hymod_mpc_t; |
| 199 | |
| 200 | /* info about high-speed (1Gbit) serial interface */ |
| 201 | typedef |
| 202 | struct { |
| 203 | unsigned char type; /* high-speed serial chip type */ |
| 204 | unsigned char nchin; /* number of input channels mounted */ |
| 205 | unsigned char nchout; /* number of output channels mounted */ |
| 206 | } |
| 207 | hymod_hss_t; |
| 208 | |
| 209 | /* |
| 210 | * this defines the contents of the serial eeprom that exists on every |
| 211 | * hymod board, including mezzanine boards (the serial eeprom will be |
| 212 | * faked for early development boards that don't have one) |
| 213 | */ |
| 214 | |
| 215 | typedef |
| 216 | struct { |
| 217 | unsigned char valid:1; /* contents of this struct is valid */ |
| 218 | unsigned char ver:7; /* eeprom contents version */ |
| 219 | unsigned char bdtype; /* board type */ |
| 220 | unsigned char bdrev; /* board revision */ |
| 221 | unsigned char batchlen; /* length of batch string below */ |
| 222 | unsigned long serno; /* serial number */ |
| 223 | hymod_date_t date; /* manufacture date */ |
| 224 | unsigned char batch[32]; /* manufacturer specific batch id */ |
| 225 | unsigned char nsdram; /* # of ram "banks" */ |
| 226 | unsigned char nflash; /* # of flash "banks" */ |
| 227 | unsigned char nzbt; /* # of ZBT rams */ |
| 228 | unsigned char nxlx; /* # of Xilinx fpgas */ |
| 229 | unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ |
| 230 | unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ |
| 231 | unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ |
| 232 | hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ |
| 233 | hymod_mpc_t mpc; /* Motorola MPC CPU info */ |
| 234 | hymod_hss_t hss; /* high-speed serial info */ |
| 235 | } |
| 236 | hymod_eeprom_t; |
| 237 | |
| 238 | /* |
| 239 | * this defines a region in the processor's physical address space |
| 240 | */ |
| 241 | typedef |
| 242 | struct { |
| 243 | unsigned long exists:1; /* 1 if the region exists, 0 if not */ |
| 244 | unsigned long size:31; /* size in bytes */ |
| 245 | unsigned long base; /* base address */ |
| 246 | } |
| 247 | xlx_prgn_t; |
| 248 | |
| 249 | /* |
| 250 | * this defines where the various Xilinx fpga access regions are mapped |
| 251 | * into the physical address space of the processor |
| 252 | */ |
| 253 | typedef |
| 254 | struct { |
| 255 | xlx_prgn_t prog; /* program access region */ |
| 256 | xlx_prgn_t reg; /* register access region */ |
| 257 | xlx_prgn_t port; /* port access region */ |
| 258 | } |
| 259 | xlx_mmap_t; |
| 260 | |
| 261 | /* |
| 262 | * this defines which 8260 i/o port pins are connected to the various |
| 263 | * signals required for programming a Xilinx fpga |
| 264 | */ |
| 265 | typedef |
| 266 | struct { |
| 267 | iopin_t prog_pin; /* assert for >= 300ns to program */ |
| 268 | iopin_t init_pin; /* goes high when fpga is cleared */ |
| 269 | iopin_t done_pin; /* goes high when program is done */ |
| 270 | iopin_t enable_pin; /* some fpgas need enabling */ |
| 271 | } |
| 272 | xlx_iopins_t; |
| 273 | |
| 274 | /* all info about one Xilinx chip */ |
| 275 | typedef |
| 276 | struct { |
| 277 | xlx_mmap_t mmap; |
| 278 | xlx_iopins_t iopins; |
| 279 | unsigned long irq:8; /* h/w intr req number for this fpga */ |
| 280 | } |
| 281 | xlx_info_t; |
| 282 | |
| 283 | /* all info about one hymod board */ |
| 284 | typedef |
| 285 | struct { |
| 286 | hymod_eeprom_t eeprom; |
| 287 | xlx_info_t xlx[HYMOD_MAX_XLX]; |
| 288 | } |
| 289 | hymod_board_t; |
| 290 | |
| 291 | /* |
| 292 | * this defines the configuration information of a hymod board-set |
| 293 | * (main board + possible mezzanine board). In future, there may be |
| 294 | * more than one mezzanine board (stackable?) - if so, add a "mezz2" |
| 295 | * field, and so on... or make mezz an array? |
| 296 | */ |
| 297 | typedef |
| 298 | struct { |
| 299 | unsigned long ver:8; /* version control */ |
| 300 | hymod_board_t main; /* main board info */ |
| 301 | hymod_board_t mezz; /* mezzanine board info */ |
| 302 | unsigned long crc; /* ensures kernel and boot prom agree */ |
| 303 | } |
| 304 | hymod_conf_t; |
| 305 | |
| 306 | #endif /* _HYMOD_H_ */ |