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wdenke2211742002-11-02 23:30:20 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenke2211742002-11-02 23:30:20 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
21#define CONFIG_IP860 1 /* ...on a IP860 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022
23#define CONFIG_SYS_TEXT_BASE 0x10000000
24
wdenkc837dcb2004-01-20 23:12:12 +000025#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050026#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenke2211742002-11-02 23:30:20 +000027
28#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29#define CONFIG_BAUDRATE 9600
30#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
31
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010032#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010033"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
wdenke2211742002-11-02 23:30:20 +000034
wdenke2211742002-11-02 23:30:20 +000035#undef CONFIG_BOOTARGS
36#define CONFIG_BOOTCOMMAND \
37 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010038 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
39 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke2211742002-11-02 23:30:20 +000040 "bootm"
41
42#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000044
45#undef CONFIG_WATCHDOG /* watchdog disabled */
46
47
48/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010049#define CONFIG_SYS_I2C
50#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
51#define CONFIG_SYS_I2C_SOFT_SPEED 50000
52#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenke2211742002-11-02 23:30:20 +000053/*
54 * Software (bit-bang) I2C driver configuration
55 */
56#define PB_SCL 0x00000020 /* PB 26 */
57#define PB_SDA 0x00000010 /* PB 27 */
58
59#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
60#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
61#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
62#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
63#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
64 else immr->im_cpm.cp_pbdat &= ~PB_SDA
65#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
66 else immr->im_cpm.cp_pbdat &= ~PB_SCL
67#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
70# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenke2211742002-11-02 23:30:20 +000071/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
73#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
74#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
wdenke2211742002-11-02 23:30:20 +000075
wdenk414eec32005-04-02 22:37:54 +000076#define CONFIG_TIMESTAMP /* Print image info with timestamp */
77
Jon Loeliger348f2582007-07-08 13:46:18 -050078
79/*
80 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_BEDBUG
85#define CONFIG_CMD_I2C
86#define CONFIG_CMD_EEPROM
87#define CONFIG_CMD_NFS
88#define CONFIG_CMD_SNTP
wdenke2211742002-11-02 23:30:20 +000089
Jon Loeliger7be044e2007-07-09 21:24:19 -050090/*
91 * BOOTP options
92 */
93#define CONFIG_BOOTP_SUBNETMASK
94#define CONFIG_BOOTP_GATEWAY
95#define CONFIG_BOOTP_HOSTNAME
96#define CONFIG_BOOTP_BOOTPATH
wdenke2211742002-11-02 23:30:20 +000097
wdenke2211742002-11-02 23:30:20 +000098/*
99 * Miscellaneous configurable options
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LONGHELP /* undef to save memory */
102#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500103#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000105#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000107#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
109#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
110#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
113#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenke2211742002-11-02 23:30:20 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000120
wdenke2211742002-11-02 23:30:20 +0000121/*
122 * Low Level Configuration Settings
123 * (address mappings, register initial values, etc.)
124 * You should know what you are doing if you make changes here.
125 */
126/*-----------------------------------------------------------------------
127 * Internal Memory Mapped Register
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */
wdenke2211742002-11-02 23:30:20 +0000130
131/*-----------------------------------------------------------------------
132 * Definitions for initial stack pointer and data area (in DPRAM)
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200135#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200136#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000138
139/*-----------------------------------------------------------------------
140 * Start addresses for the final memory configuration
141 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_SDRAM_BASE 0x00000000
145#define CONFIG_SYS_FLASH_BASE 0x10000000
wdenke2211742002-11-02 23:30:20 +0000146#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000148#else
149#if 0 /* need more space for I2C tests */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000151#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MONITOR_LEN (256 << 10)
wdenke2211742002-11-02 23:30:20 +0000153#endif
154#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
156#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000157
158/*
159 * For booting Linux, the board info and command line data
160 * have to be in the first 8 MB of memory, since this is
161 * the maximum mapped by the Linux kernel during initialization.
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000164/*-----------------------------------------------------------------------
165 * FLASH organization
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
168#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
171#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000172
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200173#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200174#undef CONFIG_ENV_IS_IN_NVRAM
175#undef CONFIG_ENV_IS_IN_NVRAM
wdenke2211742002-11-02 23:30:20 +0000176#undef DEBUG_I2C
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200177#define CONFIG_ENV_IS_IN_EEPROM
wdenke2211742002-11-02 23:30:20 +0000178
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200179#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
181#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200182#endif /* CONFIG_ENV_IS_IN_NVRAM */
wdenke2211742002-11-02 23:30:20 +0000183
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200184#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
186#define CONFIG_ENV_SIZE 1536 /* Use remaining space */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200187#endif /* CONFIG_ENV_IS_IN_EEPROM */
wdenke2211742002-11-02 23:30:20 +0000188
189/*-----------------------------------------------------------------------
190 * Cache Configuration
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500193#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000195#endif
Heiko Schocher506f3912009-03-12 07:37:15 +0100196#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
197 * running in RAM.
198 */
wdenke2211742002-11-02 23:30:20 +0000199
200/*-----------------------------------------------------------------------
201 * SYPCR - System Protection Control 11-9
202 * SYPCR can only be written once after reset!
203 *-----------------------------------------------------------------------
204 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
205 * +0x0004
206 */
207#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000209 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
210#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000212#endif
213
214/*-----------------------------------------------------------------------
215 * SIUMCR - SIU Module Configuration 11-6
216 *-----------------------------------------------------------------------
217 * +0x0000 => 0x80600800
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
wdenke2211742002-11-02 23:30:20 +0000220 SIUMCR_DBGC11 | SIUMCR_MLRC10)
221
222/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000223 * Clock Setting - get clock frequency from Board Revision Register
wdenke2211742002-11-02 23:30:20 +0000224 *-----------------------------------------------------------------------
225 */
wdenk3bac3512003-03-12 10:41:04 +0000226#ifndef __ASSEMBLY__
227extern unsigned long ip860_get_clk_freq (void);
228#endif
229#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
wdenke2211742002-11-02 23:30:20 +0000230
231/*-----------------------------------------------------------------------
232 * TBSCR - Time Base Status and Control 11-26
233 *-----------------------------------------------------------------------
234 * Clear Reference Interrupt Status, Timebase freezing enabled
235 * +0x0200 => 0x00C2
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenke2211742002-11-02 23:30:20 +0000238
239/*-----------------------------------------------------------------------
240 * PISCR - Periodic Interrupt Status and Control 11-31
241 *-----------------------------------------------------------------------
242 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
243 * +0x0240 => 0x0082
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenke2211742002-11-02 23:30:20 +0000246
247/*-----------------------------------------------------------------------
248 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
249 *-----------------------------------------------------------------------
250 * Reset PLL lock status sticky bit, timer expired status bit and timer
251 * interrupt status bit, set PLL multiplication factor !
252 */
253/* +0x0286 => was: 0x0000D000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PLPRCR \
wdenke2211742002-11-02 23:30:20 +0000255 ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
256 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
257 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
258 )
259
260/*-----------------------------------------------------------------------
261 * SCCR - System Clock and reset Control Register 15-27
262 *-----------------------------------------------------------------------
263 * Set clock output, timebase and RTC source and divider,
264 * power management and some other internal clocks
265 */
266#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
wdenke2211742002-11-02 23:30:20 +0000268 SCCR_RTDIV | SCCR_RTSEL | \
269 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
270 SCCR_EBDF00 | SCCR_DFSYNC00 | \
271 SCCR_DFBRG00 | SCCR_DFNL000 | \
272 SCCR_DFNH000)
273
274/*-----------------------------------------------------------------------
275 * RTCSC - Real-Time Clock Status and Control Register 11-27
276 *-----------------------------------------------------------------------
277 */
278/* +0x0220 => 0x00C3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000280
281
282/*-----------------------------------------------------------------------
283 * RCCR - RISC Controller Configuration Register 19-4
284 *-----------------------------------------------------------------------
285 */
286/* +0x09C4 => TIMEP=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_RCCR 0x0100
wdenke2211742002-11-02 23:30:20 +0000288
289/*-----------------------------------------------------------------------
290 * RMDS - RISC Microcode Development Support Control Register
291 *-----------------------------------------------------------------------
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_RMDS 0
wdenke2211742002-11-02 23:30:20 +0000294
295/*-----------------------------------------------------------------------
296 * DER - Debug Event Register
297 *-----------------------------------------------------------------------
298 *
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000301
302/*
303 * Init Memory Controller:
304 */
305
306/*
307 * MAMR settings for SDRAM - 16-14
308 * => 0xC3804114
309 */
310
311/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_MAMR_PTA 0xC3
wdenke2211742002-11-02 23:30:20 +0000313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000315 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
316 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
317/*
318 * BR1 and OR1 (FLASH)
319 */
320#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
321
322/* used to re-map FLASH
323 * restrict access enough to keep SRAM working (if any)
324 * but not too much to meddle with FLASH accesses
325 */
326/* allow for max 8 MB of Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
328#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
wdenke2211742002-11-02 23:30:20 +0000331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
333#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenke2211742002-11-02 23:30:20 +0000334/* 16 bit, bank valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
wdenke2211742002-11-02 23:30:20 +0000336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
338#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM
wdenke2211742002-11-02 23:30:20 +0000339
340/*
341 * BR2/OR2 - SDRAM
342 */
343#define SDRAM_BASE 0x00000000 /* SDRAM bank */
344#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
345#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
346
347#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
350#define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000351
352/*
353 * BR3/OR3 - SRAM (16 bit)
354 */
355#define SRAM_BASE 0x20000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
357#define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
358#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
359#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
360#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
Wolfgang Denk36116652010-08-11 09:38:31 +0200361#define CONFIG_SYS_SRAM_BASE SRAM_BASE
362#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE
wdenke2211742002-11-02 23:30:20 +0000363
364/*
365 * BR4/OR4 - Board Control & Status (8 bit)
366 */
367#define BCSR_BASE 0xFC000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */
369#define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000370
371/*
372 * BR5/OR5 - IP Slot A/B (16 bit)
373 */
374#define IP_SLOT_BASE 0x40000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
376#define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000377
378/*
379 * BR6/OR6 - VME STD (16 bit)
380 */
381#define VME_STD_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
383#define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000384
385/*
386 * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
387 */
388#define VME_SHORT_BASE 0xFF000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
390#define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000391
392/*-----------------------------------------------------------------------
393 * Board Control and Status Region:
394 *-----------------------------------------------------------------------
395 */
396#ifndef __ASSEMBLY__
397typedef struct ip860_bcsr_s {
398 unsigned char shmem_addr; /* +00 shared memory address register */
399 unsigned char reserved0;
400 unsigned char mbox_addr; /* +02 mailbox address register */
401 unsigned char reserved1;
402 unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
403 unsigned char reserved2;
404 unsigned char vme_int_pend; /* +06 VME interrupt pending register */
405 unsigned char reserved3;
406 unsigned char bd_int_mask; /* +08 board interrupt mask register */
407 unsigned char reserved4;
408 unsigned char bd_int_pend; /* +0A board interrupt pending register */
409 unsigned char reserved5;
410 unsigned char bd_ctrl; /* +0C board control register */
411 unsigned char reserved6;
412 unsigned char bd_status; /* +0E board status register */
413 unsigned char reserved7;
414 unsigned char vme_irq; /* +10 VME interrupt request register */
415 unsigned char reserved8;
416 unsigned char vme_ivec; /* +12 VME interrupt vector register */
417 unsigned char reserved9;
418 unsigned char cli_mbox; /* +14 clear mailbox irq */
419 unsigned char reservedA;
420 unsigned char rtc; /* +16 RTC control register */
421 unsigned char reservedB;
422 unsigned char mbox_data; /* +18 mailbox read/write register */
423 unsigned char reservedC;
424 unsigned char wd_trigger; /* +1A Watchdog trigger register */
425 unsigned char reservedD;
426 unsigned char rmw_req; /* +1C RMW request register */
wdenk3bac3512003-03-12 10:41:04 +0000427 unsigned char reservedE;
428 unsigned char bd_rev; /* +1E Board Revision register */
wdenke2211742002-11-02 23:30:20 +0000429} ip860_bcsr_t;
430#endif /* __ASSEMBLY__ */
431
432/*-----------------------------------------------------------------------
433 * Board Control Register: bd_ctrl (Offset 0x0C)
434 *-----------------------------------------------------------------------
435 */
436#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
437#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
438#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
439#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
440
wdenke2211742002-11-02 23:30:20 +0000441#endif /* __CONFIG_H */