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wdenk54387ac2003-10-08 22:45:44 +00001/*
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +01002 * Copyright (C) 2003-2005 Arabella Software Ltd.
wdenk54387ac2003-10-08 22:45:44 +00003 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
6 * This port was developed and tested on Revision C board.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk54387ac2003-10-08 22:45:44 +00009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
15#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020016
17#define CONFIG_SYS_TEXT_BASE 0xFE000000
18
wdenk54387ac2003-10-08 22:45:44 +000019#define CPU_ID_STR "MPC8265"
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050020#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk54387ac2003-10-08 22:45:44 +000021
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +010022/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
wdenk54387ac2003-10-08 22:45:44 +000023#define CONFIG_ENV_OVERWRITE
24
25/*
26 * Select serial console configuration
27 *
28 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
29 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
30 * for SCC).
31 */
32#define CONFIG_CONS_ON_SMC /* Console is on SMC */
33#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
34#undef CONFIG_CONS_NONE /* It's not on external UART */
35#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
36
37/*
38 * Select ethernet configuration
39 *
40 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
41 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
42 * SCC, 1-3 for FCC)
43 *
44 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
Jon Loeliger639221c2007-07-09 17:15:49 -050045 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
46 * must be unset.
wdenk54387ac2003-10-08 22:45:44 +000047 */
48#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
49#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
50#undef CONFIG_ETHER_NONE /* No external Ethernet */
51
52#ifdef CONFIG_ETHER_ON_FCC
53
54#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
55
56#if (CONFIG_ETHER_INDEX == 2)
57/*
58 * - Rx clock is CLK13
59 * - Tx clock is CLK14
60 * - Select bus for bd/buffers (see 28-13)
61 * - Full duplex
62 */
Mike Frysingerd4590da2011-10-17 05:38:58 +000063# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
64# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065# define CONFIG_SYS_CPMFCR_RAMTYPE 0
66# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenk54387ac2003-10-08 22:45:44 +000067
wdenk659883c2004-10-09 23:33:42 +000068#endif /* CONFIG_ETHER_INDEX */
wdenk54387ac2003-10-08 22:45:44 +000069
70#define CONFIG_MII /* MII PHY management */
71#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
72/*
73 * GPIO pins used for bit-banged MII communications
74 */
wdenk659883c2004-10-09 23:33:42 +000075#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020076#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
77 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
78#define MDC_DECLARE MDIO_DECLARE
79
wdenk659883c2004-10-09 23:33:42 +000080#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
81#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
82#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
wdenk54387ac2003-10-08 22:45:44 +000083
wdenk659883c2004-10-09 23:33:42 +000084#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
85 else iop->pdat &= ~0x00400000
wdenk54387ac2003-10-08 22:45:44 +000086
wdenk659883c2004-10-09 23:33:42 +000087#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
88 else iop->pdat &= ~0x00200000
wdenk54387ac2003-10-08 22:45:44 +000089
wdenk659883c2004-10-09 23:33:42 +000090#define MIIDELAY udelay(1)
wdenk54387ac2003-10-08 22:45:44 +000091
92#endif /* CONFIG_ETHER_ON_FCC */
93
94#ifndef CONFIG_8260_CLKIN
95#define CONFIG_8260_CLKIN 66666666 /* in Hz */
96#endif
97
wdenk659883c2004-10-09 23:33:42 +000098#define CONFIG_BAUDRATE 38400
wdenk54387ac2003-10-08 22:45:44 +000099
wdenk54387ac2003-10-08 22:45:44 +0000100
Jon Loeligera5562902007-07-08 15:31:57 -0500101/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500102 * BOOTP options
103 */
104#define CONFIG_BOOTP_BOOTFILESIZE
105#define CONFIG_BOOTP_BOOTPATH
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108
109
110/*
Jon Loeligera5562902007-07-08 15:31:57 -0500111 * Command line configuration.
112 */
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_ASKENV
116#define CONFIG_CMD_DHCP
117#define CONFIG_CMD_IMMAP
118#define CONFIG_CMD_MII
119#define CONFIG_CMD_PING
120
wdenk54387ac2003-10-08 22:45:44 +0000121
122#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
123#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
124#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
125
Jon Loeligera5562902007-07-08 15:31:57 -0500126#if defined(CONFIG_CMD_KGDB)
wdenk54387ac2003-10-08 22:45:44 +0000127#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
128#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
129#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
130#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
131#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
132#endif
133
134#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
wdenk659883c2004-10-09 23:33:42 +0000135#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
wdenk54387ac2003-10-08 22:45:44 +0000136
137/*
138 * Miscellaneous configurable options
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LONGHELP /* undef to save memory */
142#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500143#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk54387ac2003-10-08 22:45:44 +0000145#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk54387ac2003-10-08 22:45:44 +0000147#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk54387ac2003-10-08 22:45:44 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
153#define CONFIG_SYS_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
wdenk54387ac2003-10-08 22:45:44 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenk54387ac2003-10-08 22:45:44 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk54387ac2003-10-08 22:45:44 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk54387ac2003-10-08 22:45:44 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_SDRAM_SIZE 64
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_IMMR 0xF0000000
165#define CONFIG_SYS_LSDRAM_BASE 0xFC000000
166#define CONFIG_SYS_FLASH_BASE 0xFE000000
167#define CONFIG_SYS_BCSR 0xFEA00000
168#define CONFIG_SYS_EEPROM 0xFEB00000
169#define CONFIG_SYS_FLSIMM_BASE 0xFF000000
wdenk54387ac2003-10-08 22:45:44 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200172#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
174#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
wdenk54387ac2003-10-08 22:45:44 +0000177
178#define BCSR_PCI_MODE 0x01
179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200181#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200182#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk54387ac2003-10-08 22:45:44 +0000184
185/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100187 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
188 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
189 HRCW_MODCK_H0111 \
190 ) /* 0x16848207 */
wdenk54387ac2003-10-08 22:45:44 +0000191/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_HRCW_SLAVE1 0
193#define CONFIG_SYS_HRCW_SLAVE2 0
194#define CONFIG_SYS_HRCW_SLAVE3 0
195#define CONFIG_SYS_HRCW_SLAVE4 0
196#define CONFIG_SYS_HRCW_SLAVE5 0
197#define CONFIG_SYS_HRCW_SLAVE6 0
198#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk54387ac2003-10-08 22:45:44 +0000199
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200200#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Peter Tyserd98b0522010-10-14 23:33:24 -0500201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
203#define CONFIG_SYS_RAMBOOT
wdenk54387ac2003-10-08 22:45:44 +0000204#endif
205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
207#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk54387ac2003-10-08 22:45:44 +0000209
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200210#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200211#define CONFIG_ENV_IS_IN_NVRAM 1
wdenk54387ac2003-10-08 22:45:44 +0000212#endif
213
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200214#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200215# define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
wdenk54387ac2003-10-08 22:45:44 +0000217#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200219# define CONFIG_ENV_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220# define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
wdenk54387ac2003-10-08 22:45:44 +0000221#endif
222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeligera5562902007-07-08 15:31:57 -0500224#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk54387ac2003-10-08 22:45:44 +0000226#endif
227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_HID0_INIT (HID0_ICFI)
229#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
wdenk54387ac2003-10-08 22:45:44 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_HID2 0
wdenk54387ac2003-10-08 22:45:44 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SIUMCR 0x42200000
234#define CONFIG_SYS_SYPCR 0xFFFFFFC3
235#define CONFIG_SYS_BCR 0x90000000
236#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk54387ac2003-10-08 22:45:44 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_RMR RMR_CSRE
239#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
240#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
241#define CONFIG_SYS_RCCR 0
wdenk54387ac2003-10-08 22:45:44 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_PSDMR /* 0x834DA43B */0x014DA43A
244#define CONFIG_SYS_PSRT 0x0F/* 0x0C */
245#define CONFIG_SYS_LSDMR 0x0085A562
246#define CONFIG_SYS_LSRT 0x0F
247#define CONFIG_SYS_MPTPR 0x4000
wdenk54387ac2003-10-08 22:45:44 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_PSDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
250#define CONFIG_SYS_PSDRAM_OR 0xFC0028C0
251#define CONFIG_SYS_LSDRAM_BR (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
252#define CONFIG_SYS_LSDRAM_OR 0xFF803480
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00000801)
255#define CONFIG_SYS_OR0_PRELIM 0xFFE00856
256#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_EEPROM | 0x00000801)
257#define CONFIG_SYS_OR5_PRELIM 0xFFFF03F6
258#define CONFIG_SYS_BR6_PRELIM (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
259#define CONFIG_SYS_OR6_PRELIM 0xFF000856
260#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
261#define CONFIG_SYS_OR7_PRELIM 0xFFFF83F6
wdenk54387ac2003-10-08 22:45:44 +0000262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
wdenk54387ac2003-10-08 22:45:44 +0000264
265#endif /* __CONFIG_H */