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Stefan Roese6983fe22008-03-11 16:52:24 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese6983fe22008-03-11 16:52:24 +01006 */
7
8/************************************************************************
9 * canyonlands.h - configuration for Canyonlands (460EX)
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
Adam Grahamf09f09d2008-10-08 10:12:53 -070017/*
18 * This config file is used for Canyonlands (460EX) Glacier (460GT)
19 * and Arches dual (460GT)
20 */
21#ifdef CONFIG_CANYONLANDS
Stefan Roese4c9e8552008-03-19 16:20:49 +010022#define CONFIG_460EX 1 /* Specific PPC460EX */
Stefan Roese490f2042008-06-06 15:55:03 +020023#define CONFIG_HOSTNAME canyonlands
Adam Grahamf09f09d2008-10-08 10:12:53 -070024#else
25#define CONFIG_460GT 1 /* Specific PPC460GT */
26#ifdef CONFIG_GLACIER
27#define CONFIG_HOSTNAME glacier
28#else
29#define CONFIG_HOSTNAME arches
30#define CONFIG_USE_NETDEV eth1
31#define CONFIG_BD_NUM_CPUS 2
Stefan Roese4c9e8552008-03-19 16:20:49 +010032#endif
Adam Grahamf09f09d2008-10-08 10:12:53 -070033#endif
34
Stefan Roese6983fe22008-03-11 16:52:24 +010035#define CONFIG_440 1
36#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roese6983fe22008-03-11 16:52:24 +010037
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#ifndef CONFIG_SYS_TEXT_BASE
39#define CONFIG_SYS_TEXT_BASE 0xFFF80000
40#endif
41
Stefan Roese490f2042008-06-06 15:55:03 +020042/*
43 * Include common defines/options for all AMCC eval boards
44 */
45#include "amcc-common.h"
46
Stefan Roese6983fe22008-03-11 16:52:24 +010047#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
48
49#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
50#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
51#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roesecc8e8392008-03-28 14:09:04 +010052#define CONFIG_BOARD_TYPES 1 /* support board types */
Stefan Roese6983fe22008-03-11 16:52:24 +010053
54/*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
59#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
60#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
Stefan Roese6983fe22008-03-11 16:52:24 +010061
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
63#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
64#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
Stefan Roese6983fe22008-03-11 16:52:24 +010065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
67#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
68#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
69#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
Stefan Roese6983fe22008-03-11 16:52:24 +010070
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +053071/*
72 * BCSR bits as defined in the Canyonlands board user manual.
73 */
74#define BCSR_USBCTRL_OTG_RST 0x32
75#define BCSR_USBCTRL_HOST_RST 0x01
76#define BCSR_SELECT_PCIE 0x10
77
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
Stefan Roese6983fe22008-03-11 16:52:24 +010079
80/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
Stefan Roese6983fe22008-03-11 16:52:24 +010082
83/* EBC stuff */
Adam Grahamf09f09d2008-10-08 10:12:53 -070084#if !defined(CONFIG_ARCHES)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_BCSR_BASE 0xE1000000
Adam Grahamf09f09d2008-10-08 10:12:53 -070086#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
87#define CONFIG_SYS_FLASH_SIZE (64 << 20)
88#else
89#define CONFIG_SYS_FPGA_BASE 0xE1000000
90#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
91#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
92#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
93#define CONFIG_SYS_FLASH_SIZE (32 << 20)
94#endif
95
96#define CONFIG_SYS_NAND_ADDR 0xE0000000
97#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
99#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
Adam Grahamf09f09d2008-10-08 10:12:53 -0700100#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
101 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
Stefan Roese6983fe22008-03-11 16:52:24 +0100102
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600103#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
Wolfgang Denkbf560802010-09-10 23:04:05 +0200105#define CONFIG_SYS_SRAM_SIZE (256 << 10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
Stefan Roese6983fe22008-03-11 16:52:24 +0100107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
Stefan Roese41712b42008-03-05 12:31:53 +0100109
Stefan Roese6983fe22008-03-11 16:52:24 +0100110/*-----------------------------------------------------------------------
111 * Initial RAM & stack pointer (placed in OCM)
112 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200114#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200115#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese6983fe22008-03-11 16:52:24 +0100117
118/*-----------------------------------------------------------------------
119 * Serial Port
120 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +0200121#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100122
Stefan Roese6983fe22008-03-11 16:52:24 +0100123/*-----------------------------------------------------------------------
124 * Environment
125 *----------------------------------------------------------------------*/
126/*
127 * Define here the location of the environment variables (FLASH).
128 */
129#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200130#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Felix Radensky26d37f02009-06-22 15:30:42 +0300131#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
Stefan Roese6983fe22008-03-11 16:52:24 +0100133#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200134#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Felix Radensky26d37f02009-06-22 15:30:42 +0300135#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200137#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roese71665eb2008-03-03 17:27:02 +0100138#endif
139
140/*
141 * IPL (Initial Program Loader, integrated inside CPU)
142 * Will load first 4k from NAND (SPL) into cache and execute it from there.
143 *
144 * SPL (Secondary Program Loader)
145 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
146 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
147 * controller and the NAND controller so that the special U-Boot image can be
148 * loaded from NAND to SDRAM.
149 *
150 * NUB (NAND U-Boot)
151 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
152 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
153 *
154 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
155 * set up. While still running from cache, I experienced problems accessing
156 * the NAND controller. sr - 2006-08-25
Stefan Roese499e7832008-04-08 10:33:29 +0200157 *
158 * This is the first official implementation of booting from 2k page sized
159 * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
Stefan Roese71665eb2008-03-03 17:27:02 +0100160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
162#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
163#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
164#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
165#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
Stefan Roese71665eb2008-03-03 17:27:02 +0100166 /* this addr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Stefan Roese71665eb2008-03-03 17:27:02 +0100168
169/*
170 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */
173#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */
Stefan Roese71665eb2008-03-03 17:27:02 +0100174
175/*
176 * Now the NAND chip has to be defined (no autodetection used!)
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */
179#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
180#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
Stefan Roese499e7832008-04-08 10:33:29 +0200181 /* NAND chip page count */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/
183#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */
Stefan Roese71665eb2008-03-03 17:27:02 +0100184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_NAND_ECCSIZE 256
186#define CONFIG_SYS_NAND_ECCBYTES 3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_NAND_OOBSIZE 64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
Stefan Roese499e7832008-04-08 10:33:29 +0200189 48, 49, 50, 51, 52, 53, 54, 55, \
190 56, 57, 58, 59, 60, 61, 62, 63}
Stefan Roese71665eb2008-03-03 17:27:02 +0100191
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200192#ifdef CONFIG_ENV_IS_IN_NAND
Stefan Roese71665eb2008-03-03 17:27:02 +0100193/*
194 * For NAND booting the environment is embedded in the U-Boot image. Please take
195 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
198#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200199#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Stefan Roese6983fe22008-03-11 16:52:24 +0100200#endif
201
202/*-----------------------------------------------------------------------
203 * FLASH related
204 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200206#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
Stefan Roese6983fe22008-03-11 16:52:24 +0100208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
210#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
211#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese6983fe22008-03-11 16:52:24 +0100212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
214#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese6983fe22008-03-11 16:52:24 +0100215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
217#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese6983fe22008-03-11 16:52:24 +0100218
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200219#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200220#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200222#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese6983fe22008-03-11 16:52:24 +0100223
224/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200225#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
226#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200227#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese6983fe22008-03-11 16:52:24 +0100228
229/*-----------------------------------------------------------------------
230 * NAND-FLASH related
231 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
234#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese6983fe22008-03-11 16:52:24 +0100235
236/*------------------------------------------------------------------------------
237 * DDR SDRAM
238 *----------------------------------------------------------------------------*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100239#if !defined(CONFIG_NAND_U_BOOT)
Adam Grahamf09f09d2008-10-08 10:12:53 -0700240#if !defined(CONFIG_ARCHES)
Stefan Roese71665eb2008-03-03 17:27:02 +0100241/*
242 * NAND booting U-Boot version uses a fixed initialization, since the whole
243 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
244 * code.
245 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100246#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
247#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
248#define CONFIG_DDR_ECC 1 /* with ECC support */
249#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700250
251#else /* defined(CONFIG_ARCHES) */
252
253#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
254
255#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
256#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
257#undef CONFIG_PPC4xx_DDR_METHOD_A
258
259/* DDR1/2 SDRAM Device Control Register Data Values */
260/* Memory Queue */
261#define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
262#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
263#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
264#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
265#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
266#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
267#define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
268#define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
269#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
270
271/* SDRAM Controller */
272#define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
273#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
274#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
275#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
276#define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
277#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
278#define CONFIG_SYS_SDRAM0_MODT0 0x01000000
279#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
280#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
281#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
282#define CONFIG_SYS_SDRAM0_CODT 0x00800021
283#define CONFIG_SYS_SDRAM0_RTR 0x06180000
284#define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
285#define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
286#define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
287#define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
288#define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
289#define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
290#define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
291#define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
292#define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
293#define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
294#define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
295#define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
296#define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
297#define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
298#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
299#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
300#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
301#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
302#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
303#define CONFIG_SYS_SDRAM0_DLCR 0x03000091
304#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
305#define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
306#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
307#define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
308#define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
309#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
310#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
311#endif /* !defined(CONFIG_ARCHES) */
312#endif /* !defined(CONFIG_NAND_U_BOOT) */
313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
Stefan Roese6983fe22008-03-11 16:52:24 +0100315
316/*-----------------------------------------------------------------------
317 * I2C
318 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000319#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese6983fe22008-03-11 16:52:24 +0100320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_I2C_MULTI_EEPROMS
322#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
323#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
324#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
325#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese6983fe22008-03-11 16:52:24 +0100326
Stefan Roese87c0b722009-07-20 06:57:27 +0200327/* I2C bootstrap EEPROM */
Stefan Roese514bab62009-08-17 16:57:53 +0200328#if defined(CONFIG_ARCHES)
329#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
330#else
Stefan Roese87c0b722009-07-20 06:57:27 +0200331#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
Stefan Roese514bab62009-08-17 16:57:53 +0200332#endif
Stefan Roese87c0b722009-07-20 06:57:27 +0200333#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
334#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
335
Stefan Roese6983fe22008-03-11 16:52:24 +0100336/* I2C SYSMON (LM75, AD7414 is almost compatible) */
337#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
338#define CONFIG_DTT_AD7414 1 /* use AD7414 */
339#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_DTT_MAX_TEMP 70
341#define CONFIG_SYS_DTT_LOW_TEMP -30
342#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese6983fe22008-03-11 16:52:24 +0100343
Adam Grahamf09f09d2008-10-08 10:12:53 -0700344#if defined(CONFIG_ARCHES)
345#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
346#endif
347
348#if !defined(CONFIG_ARCHES)
Stefan Roese6983fe22008-03-11 16:52:24 +0100349/* RTC configuration */
350#define CONFIG_RTC_M41T62 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Adam Grahamf09f09d2008-10-08 10:12:53 -0700352#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100353
354/*-----------------------------------------------------------------------
355 * Ethernet
356 *----------------------------------------------------------------------*/
357#define CONFIG_IBM_EMAC4_V4 1
Adam Grahamf09f09d2008-10-08 10:12:53 -0700358
Stefan Roese4c9e8552008-03-19 16:20:49 +0100359#define CONFIG_HAS_ETH0
360#define CONFIG_HAS_ETH1
Adam Grahamf09f09d2008-10-08 10:12:53 -0700361
362#if !defined(CONFIG_ARCHES)
363#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
364#define CONFIG_PHY1_ADDR 1
Stefan Roese4c9e8552008-03-19 16:20:49 +0100365/* Only Glacier (460GT) has 4 EMAC interfaces */
366#ifdef CONFIG_460GT
367#define CONFIG_PHY2_ADDR 2
368#define CONFIG_PHY3_ADDR 3
369#define CONFIG_HAS_ETH2
370#define CONFIG_HAS_ETH3
371#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100372
Adam Grahamf09f09d2008-10-08 10:12:53 -0700373#else /* defined(CONFIG_ARCHES) */
374
375#define CONFIG_FIXED_PHY 0xFFFFFFFF
376#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
377#define CONFIG_PHY1_ADDR 0
378#define CONFIG_PHY2_ADDR 1
379#define CONFIG_HAS_ETH2
380
381#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
382 {devnum, speed, duplex}
383#define CONFIG_SYS_FIXED_PHY_PORTS \
384 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
385
386#define CONFIG_M88E1112_PHY
387
388/*
389 * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
390 * used by CONFIG_PHYx_ADDR
391 */
392#define CONFIG_GPCS_PHY_ADDR 0xA
393#define CONFIG_GPCS_PHY1_ADDR 0xB
394#define CONFIG_GPCS_PHY2_ADDR 0xC
395#endif /* !defined(CONFIG_ARCHES) */
396
Stefan Roese6983fe22008-03-11 16:52:24 +0100397#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
398#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
399#define CONFIG_PHY_DYNAMIC_ANEG 1
400
Stefan Roese41712b42008-03-05 12:31:53 +0100401/*-----------------------------------------------------------------------
402 * USB-OHCI
403 *----------------------------------------------------------------------*/
Stefan Roese4c9e8552008-03-19 16:20:49 +0100404/* Only Canyonlands (460EX) has USB */
405#ifdef CONFIG_460EX
Stefan Roese41712b42008-03-05 12:31:53 +0100406#define CONFIG_USB_OHCI_NEW
407#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
409#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
410#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
411#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
412#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
413#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530414#define CONFIG_SYS_USB_OHCI_BOARD_INIT
Stefan Roese4c9e8552008-03-19 16:20:49 +0100415#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100416
Stefan Roese490f2042008-06-06 15:55:03 +0200417/*
418 * Default environment variables
419 */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700420#if !defined(CONFIG_ARCHES)
421#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200422 CONFIG_AMCC_DEF_ENV \
423 CONFIG_AMCC_DEF_ENV_POWERPC \
424 CONFIG_AMCC_DEF_ENV_NOR_UPD \
425 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roese6983fe22008-03-11 16:52:24 +0100426 "kernel_addr=fc000000\0" \
Stefan Roese5d40d442008-04-22 14:14:20 +0200427 "fdt_addr=fc1e0000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100428 "ramdisk_addr=fc200000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100429 "pciconfighost=1\0" \
430 "pcie_mode=RP:RP\0" \
431 ""
Adam Grahamf09f09d2008-10-08 10:12:53 -0700432#else /* defined(CONFIG_ARCHES) */
433#define CONFIG_EXTRA_ENV_SETTINGS \
434 CONFIG_AMCC_DEF_ENV \
435 CONFIG_AMCC_DEF_ENV_POWERPC \
436 CONFIG_AMCC_DEF_ENV_NOR_UPD \
437 "kernel_addr=fe000000\0" \
438 "fdt_addr=fe1e0000\0" \
439 "ramdisk_addr=fe200000\0" \
440 "pciconfighost=1\0" \
441 "pcie_mode=RP:RP\0" \
442 "ethprime=ppc_4xx_eth1\0" \
443 ""
444#endif /* !defined(CONFIG_ARCHES) */
Stefan Roese6983fe22008-03-11 16:52:24 +0100445
446/*
Stefan Roese490f2042008-06-06 15:55:03 +0200447 * Commands additional to the ones defined in amcc-common.h
Stefan Roese6983fe22008-03-11 16:52:24 +0100448 */
Stefan Roese87c0b722009-07-20 06:57:27 +0200449#define CONFIG_CMD_CHIP_CONFIG
Adam Grahamf09f09d2008-10-08 10:12:53 -0700450#if defined(CONFIG_ARCHES)
451#define CONFIG_CMD_DTT
452#define CONFIG_CMD_PCI
453#define CONFIG_CMD_SDRAM
454#elif defined(CONFIG_CANYONLANDS)
455#define CONFIG_CMD_DATE
456#define CONFIG_CMD_DTT
457#define CONFIG_CMD_EXT2
458#define CONFIG_CMD_FAT
459#define CONFIG_CMD_NAND
460#define CONFIG_CMD_PCI
Kazuaki Ichinohee405afa2009-06-12 18:10:12 +0900461#define CONFIG_CMD_SATA
Adam Grahamf09f09d2008-10-08 10:12:53 -0700462#define CONFIG_CMD_SDRAM
463#define CONFIG_CMD_SNTP
464#define CONFIG_CMD_USB
465#elif defined(CONFIG_GLACIER)
Stefan Roese6983fe22008-03-11 16:52:24 +0100466#define CONFIG_CMD_DATE
Stefan Roese6983fe22008-03-11 16:52:24 +0100467#define CONFIG_CMD_DTT
Stefan Roese6983fe22008-03-11 16:52:24 +0100468#define CONFIG_CMD_NAND
Stefan Roese6983fe22008-03-11 16:52:24 +0100469#define CONFIG_CMD_PCI
Stefan Roese6983fe22008-03-11 16:52:24 +0100470#define CONFIG_CMD_SDRAM
Stefan Roese490f2042008-06-06 15:55:03 +0200471#define CONFIG_CMD_SNTP
Adam Grahamf09f09d2008-10-08 10:12:53 -0700472#else
473#error "board type not defined"
Stefan Roese4c9e8552008-03-19 16:20:49 +0100474#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100475
476/* Partitions */
477#define CONFIG_MAC_PARTITION
478#define CONFIG_DOS_PARTITION
479#define CONFIG_ISO_PARTITION
Stefan Roese6983fe22008-03-11 16:52:24 +0100480
481/*-----------------------------------------------------------------------
Stefan Roese6983fe22008-03-11 16:52:24 +0100482 * PCI stuff
483 *----------------------------------------------------------------------*/
484/* General PCI */
485#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000486#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese6983fe22008-03-11 16:52:24 +0100487#define CONFIG_PCI_PNP /* do pci plug-and-play */
488#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
489#define CONFIG_PCI_CONFIG_HOST_BRIDGE
490
491/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
493#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese6983fe22008-03-11 16:52:24 +0100494
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
496#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese6983fe22008-03-11 16:52:24 +0100497
Adam Grahamf09f09d2008-10-08 10:12:53 -0700498#ifdef CONFIG_460GT
499#if defined(CONFIG_ARCHES)
500/*-----------------------------------------------------------------------
501 * RapidIO I/O and Registers
502 *----------------------------------------------------------------------*/
503#define CONFIG_RAPIDIO
504#define CONFIG_SYS_460GT_SRIO_ERRATA_1
505
506#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
507#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
508#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
509#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
510#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
511
512#define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
513#define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
514#define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
515#define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
516
517#define CONFIG_SYS_I2ODMA_BASE 0xCF000000
518#define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
519
520#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
521#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
522#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
523#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
524#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
525#endif /* CONFIG_ARCHES */
526#endif /* CONFIG_460GT */
527
Kazuaki Ichinohee405afa2009-06-12 18:10:12 +0900528/*
529 * SATA driver setup
530 */
531#ifdef CONFIG_CMD_SATA
532#define CONFIG_SATA_DWC
533#define CONFIG_LIBATA
534#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
535#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
536#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
537/* Convert sectorsize to wordsize */
538#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
539#endif
540
Stefan Roese6983fe22008-03-11 16:52:24 +0100541/*-----------------------------------------------------------------------
542 * External Bus Controller (EBC) Setup
543 *----------------------------------------------------------------------*/
544
545/*
546 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
547 * boot EBC mapping only supports a maximum of 16MBytes
548 * (4.ff00.0000 - 4.ffff.ffff).
549 * To solve this problem, the FLASH has to get remapped to another
550 * EBC address which accepts bigger regions:
551 *
552 * 0xfc00.0000 -> 4.cc00.0000
Adam Grahamf09f09d2008-10-08 10:12:53 -0700553 *
554 * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
555 * remapped to:
556 *
557 * 0xfe00.0000 -> 4.ce00.0000
Stefan Roese6983fe22008-03-11 16:52:24 +0100558 */
559
Stefan Roese71665eb2008-03-03 17:27:02 +0100560#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
561/* Memory Bank 3 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_EBC_PB3AP 0x10055e00
563#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
Stefan Roese71665eb2008-03-03 17:27:02 +0100564
565/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200566#define CONFIG_SYS_EBC_PB0AP 0x018003c0
567#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100568#else
Stefan Roese6983fe22008-03-11 16:52:24 +0100569/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_EBC_PB0AP 0x10055e00
571#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
Stefan Roese6983fe22008-03-11 16:52:24 +0100572
Adam Grahamf09f09d2008-10-08 10:12:53 -0700573#if !defined(CONFIG_ARCHES)
Stefan Roese6983fe22008-03-11 16:52:24 +0100574/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575#define CONFIG_SYS_EBC_PB3AP 0x018003c0
576#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100577#endif
Adam Grahamf09f09d2008-10-08 10:12:53 -0700578#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
Stefan Roese71665eb2008-03-03 17:27:02 +0100579
Adam Grahamf09f09d2008-10-08 10:12:53 -0700580#if !defined(CONFIG_ARCHES)
Stefan Roese71665eb2008-03-03 17:27:02 +0100581/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582#define CONFIG_SYS_EBC_PB2AP 0x00804240
583#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
Stefan Roese6983fe22008-03-11 16:52:24 +0100584
Adam Grahamf09f09d2008-10-08 10:12:53 -0700585#else /* defined(CONFIG_ARCHES) */
586
587/* Memory Bank 1 (FPGA) initialization */
588#define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
589#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
590#endif /* !defined(CONFIG_ARCHES) */
591
Stefan Roese916ed942009-10-29 18:37:45 +0100592#define CONFIG_SYS_EBC_CFG 0xbfc00000
Stefan Roese6983fe22008-03-11 16:52:24 +0100593
594/*
Stefan Roese3befd852008-10-25 06:45:31 +0200595 * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
596 * pin multiplexing correctly
597 */
598#if defined(CONFIG_ARCHES)
599#define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */
600#else
601#define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */
602#endif
603
604/*
Stefan Roese6983fe22008-03-11 16:52:24 +0100605 * PPC4xx GPIO Configuration
606 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100607#ifdef CONFIG_460EX
608/* 460EX: Use USB configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100610{ \
611/* GPIO Core 0 */ \
Stefan Roese41712b42008-03-05 12:31:53 +0100612{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
613{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
614{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
615{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
616{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
617{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
618{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
619{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
620{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
621{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
622{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
623{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
624{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
625{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
626{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
627{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
628{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
629{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
630{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
631{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
632{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
633{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100634{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
635{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
636{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
637{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
638{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
639{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
640{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
641{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
642{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
643{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
644}, \
645{ \
646/* GPIO Core 1 */ \
647{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
648{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
649{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
650{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
651{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
652{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
653{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
654{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
655{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
656{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
657{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
658{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
659{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
660{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
661{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
662{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
663{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
664{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
665{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
666{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
667{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
668{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
669{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
670{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
671{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
672{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
673{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
674{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
675{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
676{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
677{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
678{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
679} \
680}
Stefan Roese4c9e8552008-03-19 16:20:49 +0100681#else
682/* 460GT: Use EMAC2+3 configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200683#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100684{ \
685/* GPIO Core 0 */ \
686{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
687{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
688{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
689{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
690{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
691{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
692{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
693{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
694{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
695{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
696{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
697{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
698{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
699{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
700{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
701{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
702{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
703{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
704{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
705{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
706{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
707{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
708{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
709{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
710{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
711{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
712{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
713{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
714{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
715{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
716{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
717{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
718}, \
719{ \
720/* GPIO Core 1 */ \
721{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
722{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
723{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
724{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
725{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
726{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
727{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
728{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
729{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
730{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
731{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
Stefan Roese3befd852008-10-25 06:45:31 +0200732{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100733{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
734{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
735{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
736{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
737{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
738{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
739{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
740{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
741{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
742{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
743{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
744{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
745{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
746{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
747{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
748{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
749{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
750{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
751{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
752{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
753} \
754}
755#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100756
Stefan Roese6983fe22008-03-11 16:52:24 +0100757#endif /* __CONFIG_H */