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Andy Fleming50586ef2008-10-30 16:47:16 -05001/*
2 * FSL SD/MMC Defines
3 *-------------------------------------------------------------------
4 *
Priyanka Jain32c8cfb2011-02-09 09:24:10 +05305 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
Andy Fleming50586ef2008-10-30 16:47:16 -05006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming50586ef2008-10-30 16:47:16 -05008 */
9
10#ifndef __FSL_ESDHC_H__
11#define __FSL_ESDHC_H__
12
Anton Vorontsovb33433a2009-06-10 00:25:29 +040013#include <asm/errno.h>
Stefano Babicc67bee12010-02-05 15:11:27 +010014#include <asm/byteorder.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040015
Andy Fleming50586ef2008-10-30 16:47:16 -050016/* FSL eSDHC-specific constants */
17#define SYSCTL 0x0002e02c
18#define SYSCTL_INITA 0x08000000
19#define SYSCTL_TIMEOUT_MASK 0x000f0000
Li Yang1118cdb2010-01-07 16:00:13 +080020#define SYSCTL_CLOCK_MASK 0x0000fff0
Stefano Babicc67bee12010-02-05 15:11:27 +010021#define SYSCTL_CKEN 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -050022#define SYSCTL_PEREN 0x00000004
23#define SYSCTL_HCKEN 0x00000002
24#define SYSCTL_IPGEN 0x00000001
Jerry Huang48bb3bb2010-03-18 15:57:06 -050025#define SYSCTL_RSTA 0x01000000
Dirk Behme7a5b8022012-03-26 03:13:05 +000026#define SYSCTL_RSTC 0x02000000
27#define SYSCTL_RSTD 0x04000000
Andy Fleming50586ef2008-10-30 16:47:16 -050028
29#define IRQSTAT 0x0002e030
30#define IRQSTAT_DMAE (0x10000000)
31#define IRQSTAT_AC12E (0x01000000)
32#define IRQSTAT_DEBE (0x00400000)
33#define IRQSTAT_DCE (0x00200000)
34#define IRQSTAT_DTOE (0x00100000)
35#define IRQSTAT_CIE (0x00080000)
36#define IRQSTAT_CEBE (0x00040000)
37#define IRQSTAT_CCE (0x00020000)
38#define IRQSTAT_CTOE (0x00010000)
39#define IRQSTAT_CINT (0x00000100)
40#define IRQSTAT_CRM (0x00000080)
41#define IRQSTAT_CINS (0x00000040)
42#define IRQSTAT_BRR (0x00000020)
43#define IRQSTAT_BWR (0x00000010)
44#define IRQSTAT_DINT (0x00000008)
45#define IRQSTAT_BGE (0x00000004)
46#define IRQSTAT_TC (0x00000002)
47#define IRQSTAT_CC (0x00000001)
48
49#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
Andrew Gabbasov9b74dc52013-04-07 23:06:08 +000050#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
51 IRQSTAT_DMAE)
52#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
Andy Fleming50586ef2008-10-30 16:47:16 -050053
54#define IRQSTATEN 0x0002e034
55#define IRQSTATEN_DMAE (0x10000000)
56#define IRQSTATEN_AC12E (0x01000000)
57#define IRQSTATEN_DEBE (0x00400000)
58#define IRQSTATEN_DCE (0x00200000)
59#define IRQSTATEN_DTOE (0x00100000)
60#define IRQSTATEN_CIE (0x00080000)
61#define IRQSTATEN_CEBE (0x00040000)
62#define IRQSTATEN_CCE (0x00020000)
63#define IRQSTATEN_CTOE (0x00010000)
64#define IRQSTATEN_CINT (0x00000100)
65#define IRQSTATEN_CRM (0x00000080)
66#define IRQSTATEN_CINS (0x00000040)
67#define IRQSTATEN_BRR (0x00000020)
68#define IRQSTATEN_BWR (0x00000010)
69#define IRQSTATEN_DINT (0x00000008)
70#define IRQSTATEN_BGE (0x00000004)
71#define IRQSTATEN_TC (0x00000002)
72#define IRQSTATEN_CC (0x00000001)
73
74#define PRSSTAT 0x0002e024
Dirk Behme7a5b8022012-03-26 03:13:05 +000075#define PRSSTAT_DAT0 (0x01000000)
Andy Fleming50586ef2008-10-30 16:47:16 -050076#define PRSSTAT_CLSL (0x00800000)
77#define PRSSTAT_WPSPL (0x00080000)
78#define PRSSTAT_CDPL (0x00040000)
79#define PRSSTAT_CINS (0x00010000)
80#define PRSSTAT_BREN (0x00000800)
Dipen Dudhat77c14582009-10-05 15:41:58 +053081#define PRSSTAT_BWEN (0x00000400)
Andy Fleming50586ef2008-10-30 16:47:16 -050082#define PRSSTAT_DLA (0x00000004)
83#define PRSSTAT_CICHB (0x00000002)
84#define PRSSTAT_CIDHB (0x00000001)
85
86#define PROCTL 0x0002e028
87#define PROCTL_INIT 0x00000020
88#define PROCTL_DTW_4 0x00000002
89#define PROCTL_DTW_8 0x00000004
90
91#define CMDARG 0x0002e008
92
93#define XFERTYP 0x0002e00c
94#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
95#define XFERTYP_CMDTYP_NORMAL 0x0
96#define XFERTYP_CMDTYP_SUSPEND 0x00400000
97#define XFERTYP_CMDTYP_RESUME 0x00800000
98#define XFERTYP_CMDTYP_ABORT 0x00c00000
99#define XFERTYP_DPSEL 0x00200000
100#define XFERTYP_CICEN 0x00100000
101#define XFERTYP_CCCEN 0x00080000
102#define XFERTYP_RSPTYP_NONE 0
103#define XFERTYP_RSPTYP_136 0x00010000
104#define XFERTYP_RSPTYP_48 0x00020000
105#define XFERTYP_RSPTYP_48_BUSY 0x00030000
106#define XFERTYP_MSBSEL 0x00000020
107#define XFERTYP_DTDSEL 0x00000010
108#define XFERTYP_AC12EN 0x00000004
109#define XFERTYP_BCEN 0x00000002
110#define XFERTYP_DMAEN 0x00000001
111
112#define CINS_TIMEOUT 1000
Dipen Dudhat77c14582009-10-05 15:41:58 +0530113#define PIO_TIMEOUT 100000
Andy Fleming50586ef2008-10-30 16:47:16 -0500114
115#define DSADDR 0x2e004
116
117#define CMDRSP0 0x2e010
118#define CMDRSP1 0x2e014
119#define CMDRSP2 0x2e018
120#define CMDRSP3 0x2e01c
121
122#define DATPORT 0x2e020
123
124#define WML 0x2e044
125#define WML_WRITE 0x00010000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530126#ifdef CONFIG_FSL_SDHC_V2_3
127#define WML_RD_WML_MAX 0x80
128#define WML_WR_WML_MAX 0x80
129#define WML_RD_WML_MAX_VAL 0x0
130#define WML_WR_WML_MAX_VAL 0x0
131#define WML_RD_WML_MASK 0x7f
132#define WML_WR_WML_MASK 0x7f0000
133#else
134#define WML_RD_WML_MAX 0x10
135#define WML_WR_WML_MAX 0x80
136#define WML_RD_WML_MAX_VAL 0x10
137#define WML_WR_WML_MAX_VAL 0x80
Roy Zangab467c52010-02-09 18:23:33 +0800138#define WML_RD_WML_MASK 0xff
139#define WML_WR_WML_MASK 0xff0000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530140#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500141
142#define BLKATTR 0x2e004
143#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
144#define BLKATTR_SIZE(x) (x & 0x1fff)
145#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
146
147#define ESDHC_HOSTCAPBLT_VS18 0x04000000
148#define ESDHC_HOSTCAPBLT_VS30 0x02000000
149#define ESDHC_HOSTCAPBLT_VS33 0x01000000
150#define ESDHC_HOSTCAPBLT_SRS 0x00800000
151#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
152#define ESDHC_HOSTCAPBLT_HSS 0x00200000
153
Stefano Babicc67bee12010-02-05 15:11:27 +0100154struct fsl_esdhc_cfg {
155 u32 esdhc_base;
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000156 u32 sdhc_clk;
Abbas Razaaad46592013-03-25 09:13:34 +0000157 u8 max_bus_width;
Stefano Babicc67bee12010-02-05 15:11:27 +0100158};
159
160/* Select the correct accessors depending on endianess */
161#if __BYTE_ORDER == __LITTLE_ENDIAN
162#define esdhc_read32 in_le32
163#define esdhc_write32 out_le32
164#define esdhc_clrsetbits32 clrsetbits_le32
165#define esdhc_clrbits32 clrbits_le32
166#define esdhc_setbits32 setbits_le32
167#elif __BYTE_ORDER == __BIG_ENDIAN
168#define esdhc_read32 in_be32
169#define esdhc_write32 out_be32
170#define esdhc_clrsetbits32 clrsetbits_be32
171#define esdhc_clrbits32 clrbits_be32
172#define esdhc_setbits32 setbits_be32
173#else
174#error "Endianess is not defined: please fix to continue"
175#endif
176
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400177#ifdef CONFIG_FSL_ESDHC
Andy Fleming50586ef2008-10-30 16:47:16 -0500178int fsl_esdhc_mmc_init(bd_t *bis);
Stefano Babicc67bee12010-02-05 15:11:27 +0100179int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400180void fdt_fixup_esdhc(void *blob, bd_t *bd);
181#else
182static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
183static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
184#endif /* CONFIG_FSL_ESDHC */
Andy Fleming50586ef2008-10-30 16:47:16 -0500185
186#endif /* __FSL_ESDHC_H__ */