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Simon Glassc65dc7d2015-08-03 08:19:27 -06001/*
2 * Copyright (C) 2012 Samsung Electronics
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <dwc3-uboot.h>
10#include <fdtdec.h>
11#include <asm/io.h>
12#include <errno.h>
13#include <i2c.h>
14#include <mmc.h>
15#include <netdev.h>
16#include <samsung-usb-phy-uboot.h>
17#include <spi.h>
18#include <usb.h>
19#include <video_bridge.h>
20#include <asm/gpio.h>
21#include <asm/arch/cpu.h>
22#include <asm/arch/dwmmc.h>
23#include <asm/arch/mmc.h>
24#include <asm/arch/pinmux.h>
25#include <asm/arch/power.h>
26#include <asm/arch/sromc.h>
27#include <power/pmic.h>
28#include <power/max77686_pmic.h>
29#include <power/regulator.h>
Przemyslaw Marczak1611c8c2015-10-27 13:08:05 +010030#include <power/s2mps11.h>
Simon Glassc65dc7d2015-08-03 08:19:27 -060031#include <power/s5m8767.h>
Przemyslaw Marczak1611c8c2015-10-27 13:08:05 +010032#include <samsung/exynos5-dt-types.h>
33#include <samsung/misc.h>
Simon Glassc65dc7d2015-08-03 08:19:27 -060034#include <tmu.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38static void board_enable_audio_codec(void)
39{
40 int node, ret;
41 struct gpio_desc en_gpio;
42
43 node = fdtdec_next_compatible(gd->fdt_blob, 0,
44 COMPAT_SAMSUNG_EXYNOS5_SOUND);
45 if (node <= 0)
46 return;
47
48 ret = gpio_request_by_name_nodev(gd->fdt_blob, node,
49 "codec-enable-gpio", 0, &en_gpio,
50 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
51 if (ret == -FDT_ERR_NOTFOUND)
52 return;
53
54 /* Turn on the GPIO which connects to the codec's "enable" line. */
55 gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE);
56
57#ifdef CONFIG_SOUND_MAX98095
58 /* Enable MAX98095 Codec */
59 gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
60 gpio_direction_output(EXYNOS5_GPIO_X17, 1);
61 gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
62#endif
63}
64
65int exynos_init(void)
66{
67 board_enable_audio_codec();
68
69 return 0;
70}
71
72static int exynos_set_regulator(const char *name, uint uv)
73{
74 struct udevice *dev;
75 int ret;
76
77 ret = regulator_get_by_platname(name, &dev);
78 if (ret) {
79 debug("%s: Cannot find regulator %s\n", __func__, name);
80 return ret;
81 }
82 ret = regulator_set_value(dev, uv);
83 if (ret) {
84 debug("%s: Cannot set regulator %s\n", __func__, name);
85 return ret;
86 }
87
88 return 0;
89}
90
91int exynos_power_init(void)
92{
93 struct udevice *dev;
94 int ret;
95
96 ret = pmic_get("max77686", &dev);
97 if (!ret) {
98 /* TODO(sjg@chromium.org): Move into the clock/pmic API */
99 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
100 MAX77686_32KHCP_EN);
101 if (ret)
102 return ret;
103 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
104 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
105 if (ret)
106 return ret;
107 } else {
108 ret = pmic_get("s5m8767-pmic", &dev);
109 /* TODO(sjg@chromium.org): Use driver model to access clock */
110#ifdef CONFIG_PMIC_S5M8767
111 if (!ret)
112 s5m8767_enable_32khz_cp(dev);
113#endif
114 }
115 if (ret == -ENODEV)
116 return 0;
117
118 ret = regulators_enable_boot_on(false);
119 if (ret)
120 return ret;
121
122 ret = exynos_set_regulator("vdd_mif", 1100000);
123 if (ret)
124 return ret;
125
126 /*
Misha Komarovskiy057d2f42015-08-25 11:53:26 +0300127 * This would normally be 1.3V, but since we are running slowly 1.1V
Simon Glassc65dc7d2015-08-03 08:19:27 -0600128 * is enough. For spring it helps reduce CPU temperature and avoid
Misha Komarovskiy057d2f42015-08-25 11:53:26 +0300129 * hangs with the case open. 1.1V is minimum voltage borderline for
130 * chained bootloaders.
Simon Glassc65dc7d2015-08-03 08:19:27 -0600131 */
Misha Komarovskiy057d2f42015-08-25 11:53:26 +0300132 ret = exynos_set_regulator("vdd_arm", 1100000);
Simon Glassc65dc7d2015-08-03 08:19:27 -0600133 if (ret)
134 return ret;
135 ret = exynos_set_regulator("vdd_int", 1012500);
136 if (ret)
137 return ret;
138 ret = exynos_set_regulator("vdd_g3d", 1200000);
139 if (ret)
140 return ret;
141
142 return 0;
143}
144
145int board_get_revision(void)
146{
147 return 0;
148}
149
150#ifdef CONFIG_LCD
151
152static int board_dp_bridge_init(struct udevice *dev)
153{
154 const int max_tries = 10;
155 int num_tries;
156 int ret;
157
158 debug("%s\n", __func__);
159 ret = video_bridge_attach(dev);
160 if (ret) {
161 debug("video bridge init failed: %d\n", ret);
162 return ret;
163 }
164
165 /*
166 * We need to wait for 90ms after bringing up the bridge since there
167 * is a phantom "high" on the HPD chip during its bootup. The phantom
168 * high comes within 7ms of de-asserting PD and persists for at least
169 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
170 * phantom high makes it hard for us to know when the NXP chip is up.
171 */
172 mdelay(90);
173
174 for (num_tries = 0; num_tries < max_tries; num_tries++) {
175 /* Check HPD. If it's high, or we don't have it, all is well */
176 ret = video_bridge_check_attached(dev);
177 if (!ret || ret == -ENOENT)
178 return 0;
179
180 debug("%s: eDP bridge failed to come up; try %d of %d\n",
181 __func__, num_tries, max_tries);
182 }
183
184 /* Immediately go into bridge reset if the hp line is not high */
185 return -EIO;
186}
187
188static int board_dp_bridge_setup(const void *blob)
189{
190 const int max_tries = 2;
191 int num_tries;
192 struct udevice *dev;
193 int ret;
194
195 /* Configure I2C registers for Parade bridge */
196 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
197 if (ret) {
198 debug("video bridge init failed: %d\n", ret);
199 return ret;
200 }
201
202 if (strncmp(dev->driver->name, "parade", 6)) {
203 /* Mux HPHPD to the special hotplug detect mode */
204 exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
205 }
206
207 for (num_tries = 0; num_tries < max_tries; num_tries++) {
208 ret = board_dp_bridge_init(dev);
209 if (!ret)
210 return 0;
211 if (num_tries == max_tries - 1)
212 break;
213
214 /*
215 * If we're here, the bridge chip failed to initialise.
216 * Power down the bridge in an attempt to reset.
217 */
218 video_bridge_set_active(dev, false);
219
220 /*
221 * Arbitrarily wait 300ms here with DP_N low. Don't know for
222 * sure how long we should wait, but we're being paranoid.
223 */
224 mdelay(300);
225 }
226
227 return ret;
228}
229
230void exynos_cfg_lcd_gpio(void)
231{
232 /* For Backlight */
233 gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
234 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
235 gpio_set_value(EXYNOS5_GPIO_B20, 1);
236}
237
238void exynos_set_dp_phy(unsigned int onoff)
239{
240 set_dp_phy_ctrl(onoff);
241}
242
243static int board_dp_set_backlight(int percent)
244{
245 struct udevice *dev;
246 int ret;
247
248 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
249 if (!ret)
250 ret = video_bridge_set_backlight(dev, percent);
251
252 return ret;
253}
254
255void exynos_backlight_on(unsigned int on)
256{
257 struct udevice *dev;
258 int ret;
259
260 debug("%s(%u)\n", __func__, on);
261 if (!on)
262 return;
263
264 ret = regulator_get_by_platname("vcd_led", &dev);
265 if (!ret)
266 ret = regulator_set_enable(dev, true);
267 if (ret)
268 debug("Failed to enable backlight: ret=%d\n", ret);
269
270 /* T5 in the LCD timing spec (defined as > 10ms) */
271 mdelay(10);
272
273 /* board_dp_backlight_pwm */
274 gpio_direction_output(EXYNOS5_GPIO_B20, 1);
275
276 /* T6 in the LCD timing spec (defined as > 10ms) */
277 mdelay(10);
278
279 /* try to set the backlight in the bridge registers */
280 ret = board_dp_set_backlight(80);
281
282 /* if we have no bridge or it does not support backlight, use a GPIO */
283 if (ret == -ENODEV || ret == -ENOSYS) {
284 gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
285 gpio_direction_output(EXYNOS5_GPIO_X30, 1);
286 }
287}
288
289void exynos_lcd_power_on(void)
290{
291 struct udevice *dev;
292 int ret;
293
294 debug("%s\n", __func__);
295 ret = regulator_get_by_platname("lcd_vdd", &dev);
296 if (!ret)
297 ret = regulator_set_enable(dev, true);
298 if (ret)
299 debug("Failed to enable LCD panel: ret=%d\n", ret);
300
301 ret = board_dp_bridge_setup(gd->fdt_blob);
302 if (ret && ret != -ENODEV)
303 printf("LCD bridge failed to enable: %d\n", ret);
304}
305
306#endif
307
308#ifdef CONFIG_USB_DWC3
309static struct dwc3_device dwc3_device_data = {
310 .maximum_speed = USB_SPEED_SUPER,
311 .base = 0x12400000,
312 .dr_mode = USB_DR_MODE_PERIPHERAL,
313 .index = 0,
314};
315
316int usb_gadget_handle_interrupts(void)
317{
318 dwc3_uboot_handle_interrupt(0);
319 return 0;
320}
321
322int board_usb_init(int index, enum usb_init_type init)
323{
324 struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
325 samsung_get_base_usb3_phy();
326
327 if (!phy) {
328 error("usb3 phy not supported");
329 return -ENODEV;
330 }
331
332 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
333 exynos5_usb3_phy_init(phy);
334
335 return dwc3_uboot_init(&dwc3_device_data);
336}
337#endif
338#ifdef CONFIG_SET_DFU_ALT_INFO
339char *get_dfu_alt_system(char *interface, char *devstr)
340{
Przemyslaw Marczak1611c8c2015-10-27 13:08:05 +0100341 char *info = "Not supported!";
342
343 if (board_is_odroidxu4())
344 return info;
345
Simon Glassc65dc7d2015-08-03 08:19:27 -0600346 return getenv("dfu_alt_system");
347}
348
349char *get_dfu_alt_boot(char *interface, char *devstr)
350{
Przemyslaw Marczak1611c8c2015-10-27 13:08:05 +0100351 char *info = "Not supported!";
Simon Glassc65dc7d2015-08-03 08:19:27 -0600352 struct mmc *mmc;
353 char *alt_boot;
354 int dev_num;
355
Przemyslaw Marczak1611c8c2015-10-27 13:08:05 +0100356 if (board_is_odroidxu4())
357 return info;
358
Simon Glassc65dc7d2015-08-03 08:19:27 -0600359 dev_num = simple_strtoul(devstr, NULL, 10);
360
361 mmc = find_mmc_device(dev_num);
362 if (!mmc)
363 return NULL;
364
365 if (mmc_init(mmc))
366 return NULL;
367
368 if (IS_SD(mmc))
369 alt_boot = CONFIG_DFU_ALT_BOOT_SD;
370 else
371 alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
372
373 return alt_boot;
374}
375#endif