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wdenk0db5bca2003-03-31 17:27:09 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
wdenk8bde7f72003-06-27 21:31:46 +00006 *
wdenk0db5bca2003-03-31 17:27:09 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * File: start.S
wdenk8bde7f72003-06-27 21:31:46 +000028 *
wdenk0db5bca2003-03-31 17:27:09 +000029 * Discription: startup code
30 *
31 */
32
33#include <config.h>
34#include <mpc5xx.h>
35#include <version.h>
36
37#define CONFIG_5xx 1 /* needed for Linux kernel header files */
38#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
39
40#include <ppc_asm.tmpl>
41#include <ppc_defs.h>
wdenk8bde7f72003-06-27 21:31:46 +000042
wdenk0db5bca2003-03-31 17:27:09 +000043#include <linux/config.h>
wdenk8bde7f72003-06-27 21:31:46 +000044#include <asm/processor.h>
wdenk0db5bca2003-03-31 17:27:09 +000045
46#ifndef CONFIG_IDENT_STRING
47#define CONFIG_IDENT_STRING ""
48#endif
49
50/* We don't have a MMU.
51*/
52#undef MSR_KERNEL
53#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
54
55/*
56 * Set up GOT: Global Offset Table
57 *
58 * Use r14 to access the GOT
59 */
60 START_GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
63
64 GOT_ENTRY(_start)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
68
wdenk3b57fe02003-05-30 12:48:29 +000069 GOT_ENTRY(__init_end)
wdenk0db5bca2003-03-31 17:27:09 +000070 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +000071 GOT_ENTRY(__bss_start)
wdenk0db5bca2003-03-31 17:27:09 +000072 END_GOT
73
74/*
75 * r3 - 1st arg to board_init(): IMMP pointer
76 * r4 - 2nd arg to board_init(): boot flag
77 */
78 .text
79 .long 0x27051956 /* U-Boot Magic Number */
80 .globl version_string
81version_string:
82 .ascii U_BOOT_VERSION
83 .ascii " (", __DATE__, " - ", __TIME__, ")"
84 .ascii CONFIG_IDENT_STRING, "\0"
85
86 . = EXC_OFF_SYS_RESET
87 .globl _start
88_start:
89 mfspr r3, 638
90 li r4, CFG_ISB /* Set ISB bit */
wdenk8bde7f72003-06-27 21:31:46 +000091 or r3, r3, r4
wdenk0db5bca2003-03-31 17:27:09 +000092 mtspr 638, r3
93 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
94 b boot_cold
95
96 . = EXC_OFF_SYS_RESET + 0x20
97
98 .globl _start_warm
99_start_warm:
100 li r21, BOOTFLAG_WARM /* Software reboot */
101 b boot_warm
102
103boot_cold:
104boot_warm:
105
106 /* Initialize machine status; enable machine check interrupt */
107 /*----------------------------------------------------------------------*/
108 li r3, MSR_KERNEL /* Set ME, RI flags */
109 mtmsr r3
110 mtspr SRR1, r3 /* Make SRR1 match MSR */
111
112 /* Initialize debug port registers */
113 /*----------------------------------------------------------------------*/
114 xor r0, r0, r0 /* Clear R0 */
115 mtspr LCTRL1, r0 /* Initialize debug port regs */
116 mtspr LCTRL2, r0
117 mtspr COUNTA, r0
118 mtspr COUNTB, r0
119
wdenkb6e4c402004-01-02 16:05:07 +0000120#if defined(CONFIG_PATI)
121 /* the external flash access on PATI fails if programming the PLL to 40MHz.
122 * Copy the PLL programming code to the internal RAM and execute it
123 *----------------------------------------------------------------------*/
124 lis r3, CFG_MONITOR_BASE@h
125 ori r3, r3, CFG_MONITOR_BASE@l
126 addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
127
128 lis r4, CFG_INIT_RAM_ADDR@h
129 ori r4, r4, CFG_INIT_RAM_ADDR@l
130 mtlr r4
131 addis r5,0,0x0
132 ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
133 mtctr r5
134 addi r3, r3, -4
135 addi r4, r4, -4
1360:
137 lwzu r0,4(r3)
138 stwu r0,4(r4)
139 bdnz 0b /* copy loop */
140 blrl
141#endif
142
wdenk0db5bca2003-03-31 17:27:09 +0000143 /*
144 * Calculate absolute address in FLASH and jump there
145 *----------------------------------------------------------------------*/
146
147 lis r3, CFG_MONITOR_BASE@h
148 ori r3, r3, CFG_MONITOR_BASE@l
149 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
150 mtlr r3
151 blr
152
153in_flash:
154
155 /* Initialize some SPRs that are hard to access from C */
156 /*----------------------------------------------------------------------*/
wdenk8bde7f72003-06-27 21:31:46 +0000157
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200158 lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
wdenk0db5bca2003-03-31 17:27:09 +0000159 lis r2, CFG_INIT_SP_ADDR@h
160 ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
161 /* Note: R0 is still 0 here */
162 stwu r0, -4(r1) /* Clear final stack frame so that */
163 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
164
165 /*
166 * Disable serialized ifetch and show cycles
167 * (i.e. set processor to normal mode) for maximum
168 * performance.
169 */
170
171 li r2, 0x0007
172 mtspr ICTRL, r2
173
174 /* Set up debug mode entry */
175
176 lis r2, CFG_DER@h
177 ori r2, r2, CFG_DER@l
178 mtspr DER, r2
179
180 /* Let the C-code set up the rest */
181 /* */
182 /* Be careful to keep code relocatable ! */
183 /*----------------------------------------------------------------------*/
184
185 GET_GOT /* initialize GOT access */
186
187 /* r3: IMMR */
188 bl cpu_init_f /* run low-level CPU init code (from Flash) */
189
190 mr r3, r21
191 /* r3: BOOTFLAG */
192 bl board_init_f /* run 1st part of board init code (from Flash) */
193
194
wdenk0db5bca2003-03-31 17:27:09 +0000195 .globl _start_of_vectors
196_start_of_vectors:
197
198/* Machine check */
199 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
200
201/* Data Storage exception. "Never" generated on the 860. */
202 STD_EXCEPTION(0x300, DataStorage, UnknownException)
203
204/* Instruction Storage exception. "Never" generated on the 860. */
205 STD_EXCEPTION(0x400, InstStorage, UnknownException)
206
207/* External Interrupt exception. */
208 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
209
210/* Alignment exception. */
211 . = 0x600
212Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200213 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk0db5bca2003-03-31 17:27:09 +0000214 mfspr r4,DAR
215 stw r4,_DAR(r21)
216 mfspr r5,DSISR
217 stw r5,_DSISR(r21)
218 addi r3,r1,STACK_FRAME_OVERHEAD
219 li r20,MSR_KERNEL
220 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
221 lwz r6,GOT(transfer_to_handler)
222 mtlr r6
223 blrl
224.L_Alignment:
225 .long AlignmentException - _start + EXC_OFF_SYS_RESET
226 .long int_return - _start + EXC_OFF_SYS_RESET
227
228/* Program check exception */
229 . = 0x700
230ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200231 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk0db5bca2003-03-31 17:27:09 +0000232 addi r3,r1,STACK_FRAME_OVERHEAD
233 li r20,MSR_KERNEL
234 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
235 lwz r6,GOT(transfer_to_handler)
236 mtlr r6
237 blrl
238.L_ProgramCheck:
239 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
240 .long int_return - _start + EXC_OFF_SYS_RESET
241
242 /* FPU on MPC5xx available. We will use it later.
243 */
244 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
245
246 /* I guess we could implement decrementer, and may have
247 * to someday for timekeeping.
248 */
249 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
250 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
251 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000252 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenk0db5bca2003-03-31 17:27:09 +0000253 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
254
255 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
256 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
257
258 /* On the MPC8xx, this is a software emulation interrupt. It occurs
259 * for all unimplemented and illegal instructions.
260 */
261 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
262 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
263 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
264 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
265 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
266
267 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
268 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
269 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
270 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
271 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
272 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
273 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
274
275 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
276 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
277 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
278 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
279
280
281 .globl _end_of_vectors
282_end_of_vectors:
283
284
285 . = 0x2000
286
287/*
288 * This code finishes saving the registers to the exception frame
289 * and jumps to the appropriate handler for the exception.
290 * Register r21 is pointer into trap frame, r1 has new stack pointer.
291 */
292 .globl transfer_to_handler
293transfer_to_handler:
294 stw r22,_NIP(r21)
295 lis r22,MSR_POW@h
296 andc r23,r23,r22
297 stw r23,_MSR(r21)
298 SAVE_GPR(7, r21)
299 SAVE_4GPRS(8, r21)
300 SAVE_8GPRS(12, r21)
301 SAVE_8GPRS(24, r21)
302 mflr r23
303 andi. r24,r23,0x3f00 /* get vector offset */
304 stw r24,TRAP(r21)
305 li r22,0
306 stw r22,RESULT(r21)
307 mtspr SPRG2,r22 /* r1 is now kernel sp */
308 lwz r24,0(r23) /* virtual address of handler */
309 lwz r23,4(r23) /* where to go when done */
310 mtspr SRR0,r24
311 mtspr SRR1,r20
312 mtlr r23
313 SYNC
314 rfi /* jump to handler, enable MMU */
315
316int_return:
317 mfmsr r28 /* Disable interrupts */
318 li r4,0
319 ori r4,r4,MSR_EE
320 andc r28,r28,r4
321 SYNC /* Some chip revs need this... */
322 mtmsr r28
323 SYNC
324 lwz r2,_CTR(r1)
325 lwz r0,_LINK(r1)
326 mtctr r2
327 mtlr r0
328 lwz r2,_XER(r1)
329 lwz r0,_CCR(r1)
330 mtspr XER,r2
331 mtcrf 0xFF,r0
332 REST_10GPRS(3, r1)
333 REST_10GPRS(13, r1)
334 REST_8GPRS(23, r1)
335 REST_GPR(31, r1)
336 lwz r2,_NIP(r1) /* Restore environment */
337 lwz r0,_MSR(r1)
338 mtspr SRR0,r2
339 mtspr SRR1,r0
340 lwz r0,GPR0(r1)
341 lwz r2,GPR2(r1)
342 lwz r1,GPR1(r1)
343 SYNC
344 rfi
345
wdenk8bde7f72003-06-27 21:31:46 +0000346
wdenk0db5bca2003-03-31 17:27:09 +0000347/*
348 * unsigned int get_immr (unsigned int mask)
349 *
350 * return (mask ? (IMMR & mask) : IMMR);
351 */
352 .globl get_immr
353get_immr:
354 mr r4,r3 /* save mask */
355 mfspr r3, IMMR /* IMMR */
356 cmpwi 0,r4,0 /* mask != 0 ? */
357 beq 4f
358 and r3,r3,r4 /* IMMR & mask */
3594:
360 blr
361
362 .globl get_pvr
363get_pvr:
364 mfspr r3, PVR
365 blr
366
367
368/*------------------------------------------------------------------------------*/
369
370/*
371 * void relocate_code (addr_sp, gd, addr_moni)
372 *
373 * This "function" does not return, instead it continues in RAM
374 * after relocating the monitor code.
375 *
376 * r3 = dest
377 * r4 = src
378 * r5 = length in bytes
379 * r6 = cachelinesize
380 */
381 .globl relocate_code
382relocate_code:
383 mr r1, r3 /* Set new stack pointer in SRAM */
384 mr r9, r4 /* Save copy of global data pointer in SRAM */
385 mr r10, r5 /* Save copy of monitor destination Address in SRAM */
386
387 mr r3, r5 /* Destination Address */
388 lis r4, CFG_MONITOR_BASE@h /* Source Address */
389 ori r4, r4, CFG_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000390 lwz r5, GOT(__init_end)
391 sub r5, r5, r4
wdenk0db5bca2003-03-31 17:27:09 +0000392
393 /*
394 * Fix GOT pointer:
395 *
396 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
397 *
398 * Offset:
399 */
400 sub r15, r10, r4
401
402 /* First our own GOT */
403 add r14, r14, r15
404 /* the the one used by the C code */
405 add r30, r30, r15
406
407 /*
408 * Now relocate code
409 */
410
411 cmplw cr1,r3,r4
412 addi r0,r5,3
413 srwi. r0,r0,2
414 beq cr1,4f /* In place copy is not necessary */
415 beq 4f /* Protect against 0 count */
416 mtctr r0
417 bge cr1,2f
418
419 la r8,-4(r4)
420 la r7,-4(r3)
4211: lwzu r0,4(r8)
422 stwu r0,4(r7)
423 bdnz 1b
424 b 4f
425
4262: slwi r0,r0,2
427 add r8,r4,r0
428 add r7,r3,r0
4293: lwzu r0,-4(r8)
430 stwu r0,-4(r7)
431 bdnz 3b
432
wdenk8bde7f72003-06-27 21:31:46 +00004334: sync
wdenk0db5bca2003-03-31 17:27:09 +0000434 isync
435
436/*
437 * We are done. Do not return, instead branch to second part of board
438 * initialization, now running from RAM.
439 */
440
441 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
442 mtlr r0
443 blr
444
445in_ram:
446
447 /*
448 * Relocation Function, r14 point to got2+0x8000
449 *
wdenk8bde7f72003-06-27 21:31:46 +0000450 * Adjust got2 pointers, no need to check for 0, this code
451 * already puts a few entries in the table.
wdenk0db5bca2003-03-31 17:27:09 +0000452 */
453 li r0,__got2_entries@sectoff@l
454 la r3,GOT(_GOT2_TABLE_)
455 lwz r11,GOT(_GOT2_TABLE_)
456 mtctr r0
457 sub r11,r3,r11
458 addi r3,r3,-4
4591: lwzu r0,4(r3)
460 add r0,r0,r11
461 stw r0,0(r3)
462 bdnz 1b
463
464 /*
wdenk8bde7f72003-06-27 21:31:46 +0000465 * Now adjust the fixups and the pointers to the fixups
wdenk0db5bca2003-03-31 17:27:09 +0000466 * in case we need to move ourselves again.
467 */
4682: li r0,__fixup_entries@sectoff@l
469 lwz r3,GOT(_FIXUP_TABLE_)
470 cmpwi r0,0
471 mtctr r0
472 addi r3,r3,-4
473 beq 4f
4743: lwzu r4,4(r3)
475 lwzux r0,r4,r11
476 add r0,r0,r11
477 stw r10,0(r3)
478 stw r0,0(r4)
479 bdnz 3b
4804:
481clear_bss:
482 /*
483 * Now clear BSS segment
484 */
wdenk5d232d02003-05-22 22:52:13 +0000485 lwz r3,GOT(__bss_start)
wdenk0db5bca2003-03-31 17:27:09 +0000486 lwz r4,GOT(_end)
487 cmplw 0, r3, r4
488 beq 6f
489
490 li r0, 0
4915:
492 stw r0, 0(r3)
493 addi r3, r3, 4
494 cmplw 0, r3, r4
495 bne 5b
4966:
497
498 mr r3, r9 /* Global Data pointer */
499 mr r4, r10 /* Destination Address */
500 bl board_init_r
501
wdenk0db5bca2003-03-31 17:27:09 +0000502 /*
503 * Copy exception vector code to low memory
504 *
505 * r3: dest_addr
506 * r7: source address, r8: end address, r9: target address
507 */
508 .globl trap_init
509trap_init:
510 lwz r7, GOT(_start)
511 lwz r8, GOT(_end_of_vectors)
512
wdenk682011f2003-06-03 23:54:09 +0000513 li r9, 0x100 /* reset vector always at 0x100 */
wdenk0db5bca2003-03-31 17:27:09 +0000514
515 cmplw 0, r7, r8
516 bgelr /* return if r7>=r8 - just in case */
517
518 mflr r4 /* save link register */
5191:
520 lwz r0, 0(r7)
521 stw r0, 0(r9)
522 addi r7, r7, 4
523 addi r9, r9, 4
524 cmplw 0, r7, r8
525 bne 1b
526
527 /*
528 * relocate `hdlr' and `int_return' entries
529 */
530 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
531 li r8, Alignment - _start + EXC_OFF_SYS_RESET
5322:
533 bl trap_reloc
534 addi r7, r7, 0x100 /* next exception vector */
535 cmplw 0, r7, r8
536 blt 2b
537
538 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
539 bl trap_reloc
540
541 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
542 bl trap_reloc
543
544 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
545 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
5463:
547 bl trap_reloc
548 addi r7, r7, 0x100 /* next exception vector */
549 cmplw 0, r7, r8
550 blt 3b
551
552 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
553 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
5544:
555 bl trap_reloc
556 addi r7, r7, 0x100 /* next exception vector */
557 cmplw 0, r7, r8
558 blt 4b
559
560 mtlr r4 /* restore link register */
561 blr
562
563 /*
564 * Function: relocate entries for one exception vector
565 */
566trap_reloc:
567 lwz r0, 0(r7) /* hdlr ... */
568 add r0, r0, r3 /* ... += dest_addr */
569 stw r0, 0(r7)
570
571 lwz r0, 4(r7) /* int_return ... */
572 add r0, r0, r3 /* ... += dest_addr */
573 stw r0, 4(r7)
574
575 sync
576 isync
577
578 blr
wdenkb6e4c402004-01-02 16:05:07 +0000579
580
581#if defined(CONFIG_PATI)
582/* Program the PLL */
583pll_prog_code_start:
584 lis r4, (CFG_IMMR + 0x002fc384)@h
585 ori r4, r4, (CFG_IMMR + 0x002fc384)@l
586 lis r3, (0x55ccaa33)@h
587 ori r3, r3, (0x55ccaa33)@l
588 stw r3, 0(r4)
589 lis r4, (CFG_IMMR + 0x002fc284)@h
590 ori r4, r4, (CFG_IMMR + 0x002fc284)@l
591 lis r3, CFG_PLPRCR@h
592 ori r3, r3, CFG_PLPRCR@l
593 stw r3, 0(r4)
594 addis r3,0,0x0
595 ori r3,r3,0xA000
596 mtctr r3
597..spinlp:
598 bdnz ..spinlp /* spin loop */
599 blr
600pll_prog_code_end:
601 nop
602 blr
603#endif