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wdenkaffae2b2002-08-17 09:36:01 +00001/*-----------------------------------------------------------------------------+
2 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +02003 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
wdenkaffae2b2002-08-17 09:36:01 +00009 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020010 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
wdenkaffae2b2002-08-17 09:36:01 +000013 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020014 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
wdenkaffae2b2002-08-17 09:36:01 +000017 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020018 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkaffae2b2002-08-17 09:36:01 +000020 +-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020023 | File Name: miiphy.c
wdenkaffae2b2002-08-17 09:36:01 +000024 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020025 | Function: This module has utilities for accessing the MII PHY through
wdenkaffae2b2002-08-17 09:36:01 +000026 | the EMAC3 macro.
27 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020028 | Author: Mark Wisner
wdenkaffae2b2002-08-17 09:36:01 +000029 |
30 | Change Activity-
31 |
Stefan Roesed6c61aa2005-08-16 18:18:00 +020032 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
35 | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
36 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
40 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
41 | <travis.sawyer@sandburst.com>
wdenkaffae2b2002-08-17 09:36:01 +000042 |
43 +-----------------------------------------------------------------------------*/
44
45#include <common.h>
46#include <asm/processor.h>
47#include <ppc_asm.tmpl>
48#include <commproc.h>
Stefan Roesed6c61aa2005-08-16 18:18:00 +020049#include <ppc4xx_enet.h>
wdenkaffae2b2002-08-17 09:36:01 +000050#include <405_mal.h>
51#include <miiphy.h>
52
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020053#undef ET_DEBUG
wdenkaffae2b2002-08-17 09:36:01 +000054/***********************************************************/
Stefan Roesed6c61aa2005-08-16 18:18:00 +020055/* Dump out to the screen PHY regs */
wdenkaffae2b2002-08-17 09:36:01 +000056/***********************************************************/
57
Marian Balakowicz63ff0042005-10-28 22:30:33 +020058void miiphy_dump (char *devname, unsigned char addr)
wdenkaffae2b2002-08-17 09:36:01 +000059{
60 unsigned long i;
61 unsigned short data;
62
63
64 for (i = 0; i < 0x1A; i++) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +020065 if (miiphy_read (devname, addr, i, &data)) {
wdenkaffae2b2002-08-17 09:36:01 +000066 printf ("read error for reg %lx\n", i);
67 return;
68 }
69 printf ("Phy reg %lx ==> %4x\n", i, data);
70
71 /* jump to the next set of regs */
72 if (i == 0x07)
73 i = 0x0f;
74
Stefan Roesed6c61aa2005-08-16 18:18:00 +020075 } /* end for loop */
76} /* end dump */
wdenkaffae2b2002-08-17 09:36:01 +000077
78
wdenkaffae2b2002-08-17 09:36:01 +000079/***********************************************************/
Stefan Roesed6c61aa2005-08-16 18:18:00 +020080/* (Re)start autonegotiation */
wdenkaffae2b2002-08-17 09:36:01 +000081/***********************************************************/
Marian Balakowicz63ff0042005-10-28 22:30:33 +020082int phy_setup_aneg (char *devname, unsigned char addr)
wdenkaffae2b2002-08-17 09:36:01 +000083{
Stefan Roesed6c61aa2005-08-16 18:18:00 +020084 unsigned short ctl, adv;
wdenkaffae2b2002-08-17 09:36:01 +000085
Stefan Roesed6c61aa2005-08-16 18:18:00 +020086 /* Setup standard advertise */
Marian Balakowicz63ff0042005-10-28 22:30:33 +020087 miiphy_read (devname, addr, PHY_ANAR, &adv);
Stefan Roesed6c61aa2005-08-16 18:18:00 +020088 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
89 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
90 PHY_ANLPAR_10);
Marian Balakowicz63ff0042005-10-28 22:30:33 +020091 miiphy_write (devname, addr, PHY_ANAR, adv);
Stefan Roesed6c61aa2005-08-16 18:18:00 +020092
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020093 miiphy_read (devname, addr, PHY_1000BTCR, &adv);
94 adv |= (0x0300);
95 miiphy_write (devname, addr, PHY_1000BTCR, adv);
96
Stefan Roesed6c61aa2005-08-16 18:18:00 +020097 /* Start/Restart aneg */
Marian Balakowicz63ff0042005-10-28 22:30:33 +020098 miiphy_read (devname, addr, PHY_BMCR, &ctl);
Stefan Roesed6c61aa2005-08-16 18:18:00 +020099 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200100 miiphy_write (devname, addr, PHY_BMCR, ctl);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200101
102 return 0;
103}
104
105
106/***********************************************************/
107/* read a phy reg and return the value with a rc */
108/***********************************************************/
109unsigned int miiphy_getemac_offset (void)
110{
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200111#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200112 unsigned long zmii;
113 unsigned long eoffset;
114
115 /* Need to find out which mdi port we're using */
116 zmii = in32 (ZMII_FER);
117
118 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
119 /* using port 0 */
120 eoffset = 0;
121 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
122 /* using port 1 */
123 eoffset = 0x100;
124 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
125 /* using port 2 */
126 eoffset = 0x400;
127 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
128 /* using port 3 */
129 eoffset = 0x600;
130 } else {
131 /* None of the mdi ports are enabled! */
132 /* enable port 0 */
133 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
134 out32 (ZMII_FER, zmii);
135 eoffset = 0;
136 /* need to soft reset port 0 */
137 zmii = in32 (EMAC_M0);
138 zmii |= EMAC_M0_SRST;
139 out32 (EMAC_M0, zmii);
140 }
141
142 return (eoffset);
143#else
144 return 0;
145#endif
146}
147
148
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200149int emac4xx_miiphy_read (char *devname, unsigned char addr,
150 unsigned char reg, unsigned short *value)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200151{
152 unsigned long sta_reg; /* STA scratch area */
153 unsigned long i;
154 unsigned long emac_reg;
155
156
157 emac_reg = miiphy_getemac_offset ();
wdenkaffae2b2002-08-17 09:36:01 +0000158 /* see if it is ready for 1000 nsec */
159 i = 0;
160
161 /* see if it is ready for sec */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200162 while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
wdenkaffae2b2002-08-17 09:36:01 +0000163 udelay (7);
164 if (i > 5) {
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200165#ifdef ET_DEBUG
166 sta_reg = in32 (EMAC_STACR + emac_reg);
167 printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
wdenkaffae2b2002-08-17 09:36:01 +0000168 printf ("read err 1\n");
stroese38a95192003-12-09 14:57:03 +0000169#endif
wdenkaffae2b2002-08-17 09:36:01 +0000170 return -1;
171 }
172 i++;
173 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200174 sta_reg = reg; /* reg address */
wdenkaffae2b2002-08-17 09:36:01 +0000175 /* set clock (50Mhz) and read flags */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200176#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
177 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200178#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
179 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
180#else
181 sta_reg |= EMAC_STACR_READ;
182#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200183#else
wdenkaffae2b2002-08-17 09:36:01 +0000184 sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200185#endif
186
Stefan Roese887e2ec2006-09-07 11:51:23 +0200187#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
188 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
189 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
wdenk12f34242003-09-02 22:48:03 +0000190 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
wdenk093ae272003-09-02 23:08:13 +0000191#endif
wdenkaffae2b2002-08-17 09:36:01 +0000192 sta_reg = sta_reg | (addr << 5); /* Phy address */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200193 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200194 out32 (EMAC_STACR + emac_reg, sta_reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200195#ifdef ET_DEBUG
wdenkaffae2b2002-08-17 09:36:01 +0000196 printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
197#endif
198
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200199 sta_reg = in32 (EMAC_STACR + emac_reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200200#ifdef ET_DEBUG
201 printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
202#endif
wdenkaffae2b2002-08-17 09:36:01 +0000203 i = 0;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200204 while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
wdenkaffae2b2002-08-17 09:36:01 +0000205 udelay (7);
206 if (i > 5) {
wdenkaffae2b2002-08-17 09:36:01 +0000207 return -1;
208 }
209 i++;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200210 sta_reg = in32 (EMAC_STACR + emac_reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200211#ifdef ET_DEBUG
212 printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
213#endif
wdenkaffae2b2002-08-17 09:36:01 +0000214 }
215 if ((sta_reg & EMAC_STACR_PHYE) != 0) {
wdenkaffae2b2002-08-17 09:36:01 +0000216 return -1;
217 }
218
219 *value = *(short *) (&sta_reg);
220 return 0;
221
222
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200223} /* phy_read */
wdenkaffae2b2002-08-17 09:36:01 +0000224
225
226/***********************************************************/
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200227/* write a phy reg and return the value with a rc */
wdenkaffae2b2002-08-17 09:36:01 +0000228/***********************************************************/
229
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200230int emac4xx_miiphy_write (char *devname, unsigned char addr,
231 unsigned char reg, unsigned short value)
wdenkaffae2b2002-08-17 09:36:01 +0000232{
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200233 unsigned long sta_reg; /* STA scratch area */
wdenkaffae2b2002-08-17 09:36:01 +0000234 unsigned long i;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200235 unsigned long emac_reg;
wdenkaffae2b2002-08-17 09:36:01 +0000236
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200237 emac_reg = miiphy_getemac_offset ();
wdenkaffae2b2002-08-17 09:36:01 +0000238 /* see if it is ready for 1000 nsec */
239 i = 0;
240
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200241 while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
wdenkaffae2b2002-08-17 09:36:01 +0000242 if (i > 5)
243 return -1;
244 udelay (7);
245 i++;
246 }
247 sta_reg = 0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200248 sta_reg = reg; /* reg address */
wdenkaffae2b2002-08-17 09:36:01 +0000249 /* set clock (50Mhz) and read flags */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200250#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
251 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200252#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
253 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
254#else
255 sta_reg |= EMAC_STACR_WRITE;
256#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200257#else
wdenkaffae2b2002-08-17 09:36:01 +0000258 sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200259#endif
260
Stefan Roese887e2ec2006-09-07 11:51:23 +0200261#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
262 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
263 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200264 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
wdenk093ae272003-09-02 23:08:13 +0000265#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200266 sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
267 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
wdenkaffae2b2002-08-17 09:36:01 +0000268 memcpy (&sta_reg, &value, 2); /* put in data */
269
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200270 out32 (EMAC_STACR + emac_reg, sta_reg);
wdenkaffae2b2002-08-17 09:36:01 +0000271
wdenkaffae2b2002-08-17 09:36:01 +0000272 /* wait for completion */
273 i = 0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200274 sta_reg = in32 (EMAC_STACR + emac_reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200275#ifdef ET_DEBUG
276 printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
277#endif
278 while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
wdenkaffae2b2002-08-17 09:36:01 +0000279 udelay (7);
280 if (i > 5)
281 return -1;
282 i++;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200283 sta_reg = in32 (EMAC_STACR + emac_reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200284#ifdef ET_DEBUG
285 printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
286#endif
wdenkaffae2b2002-08-17 09:36:01 +0000287 }
288
289 if ((sta_reg & EMAC_STACR_PHYE) != 0)
290 return -1;
291 return 0;
292
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200293} /* phy_write */