| Stefan Roese | 62534be | 2006-03-17 10:28:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2006 |
| 6 | * DAVE Srl <www.dave-tech.it> |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #ifndef _SDRAM_H_ |
| 28 | #define _SDRAM_H_ |
| 29 | |
| 30 | #include <config.h> |
| 31 | |
| 32 | #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) |
| 33 | |
| 34 | #define ONE_BILLION 1000000000 |
| 35 | |
| 36 | struct sdram_conf_s { |
| 37 | unsigned long size; |
| 38 | int rows; |
| 39 | unsigned long reg; |
| 40 | }; |
| 41 | |
| 42 | typedef struct sdram_conf_s sdram_conf_t; |
| 43 | |
| 44 | /* Bitfields offsets */ |
| 45 | #define SDRAM0_TR_CASL (31 - 8) |
| 46 | #define SDRAM0_TR_PTA (31 - 13) |
| 47 | #define SDRAM0_TR_CTP (31 - 15) |
| 48 | #define SDRAM0_TR_LDF (31 - 17) |
| 49 | #define SDRAM0_TR_RFTA (31 - 29) |
| 50 | #define SDRAM0_TR_RCD (31 - 31) |
| 51 | |
| 52 | #ifdef CFG_SDRAM_CL |
| 53 | /* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */ |
| 54 | #define CFG_SDRAM_CASL CFG_SDRAM_CL |
| 55 | #define CFG_SDRAM_PTA CFG_SDRAM_tRP |
| 56 | #define CFG_SDRAM_CTP (CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP) |
| 57 | #define CFG_SDRAM_LDF 0 |
| 58 | #ifdef CFG_SDRAM_tRFC |
| 59 | #define CFG_SDRAM_RFTA CFG_SDRAM_tRFC |
| 60 | #else |
| 61 | #define CFG_SDRAM_RFTA CFG_SDRAM_tRC |
| 62 | #endif |
| 63 | #define CFG_SDRAM_RCD CFG_SDRAM_tRCD |
| 64 | #endif /* #ifdef CFG_SDRAM_CL */ |
| 65 | |
| 66 | /* |
| 67 | * Some defines for the 440 DDR controller |
| 68 | */ |
| 69 | #define SDRAM_CFG0_DC_EN 0x80000000 /* SDRAM Controller Enable */ |
| 70 | #define SDRAM_CFG0_MEMCHK 0x30000000 /* Memory data error checking mask*/ |
| 71 | #define SDRAM_CFG0_MEMCHK_NON 0x00000000 /* No ECC generation */ |
| 72 | #define SDRAM_CFG0_MEMCHK_GEN 0x20000000 /* ECC generation */ |
| 73 | #define SDRAM_CFG0_MEMCHK_CHK 0x30000000 /* ECC generation and checking */ |
| 74 | #define SDRAM_CFG0_DRAMWDTH 0x02000000 /* DRAM width mask */ |
| 75 | #define SDRAM_CFG0_DRAMWDTH_32 0x00000000 /* 32 bits */ |
| 76 | #define SDRAM_CFG0_DRAMWDTH_64 0x02000000 /* 64 bits */ |
| 77 | |
| 78 | #endif |