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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / afabb498b749b48ca3ee7e833fe1501e2d6993cb / . / board / amcc / katmai / init.S
blob: 59ccf2b6aa694c4141f691c210566387c213cd57 [file] [log] [blame]
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <ppc_asm.tmpl>
27#include <config.h>
Peter Tyser61f2b382010-04-12 22:28:07 -0500[diff] [blame]28#include <asm/mmu.h>
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]29
30/**************************************************************************
31 * TLB TABLE
32 *
33 * This table is used by the cpu boot code to setup the initial tlb
34 * entries. Rather than make broad assumptions in the cpu source tree,
35 * this table lets each board set things up however they like.
36 *
37 * Pointer to the table is returned in r1
38 *
39 *************************************************************************/
40
41 .section .bootpg,"ax"
42
43/**************************************************************************
44 * TLB table for revA
45 *************************************************************************/
46 .globl tlbtabA
47tlbtabA:
48 tlbtab_start
Stefan Roese2721a682007-03-08 10:07:18 +0100[diff] [blame]49
50 /*
51 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
52 * speed up boot process. It is patched after relocation to enable SA_I
53 */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]54 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]55
56 /*
57 * TLB entries for SDRAM are not needed on this platform.
58 * They are dynamically generated in the SPD DDR(2) detection
59 * routine.
60 */
61
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]62 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
63 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]64
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]65 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
66 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
67 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
68 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]69
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]70 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
71 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
72 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
73 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
74 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
75 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]76 tlbtab_end
77
78/**************************************************************************
79 * TLB table for revB
80 *
81 * Notice: revB of the 440SPe chip is very strict about PLB real addresses
82 * and ranges to be mapped for config space: it seems to only work with
83 * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
84 * set otherwise) while revA uses c_nnnn_nnnn.
85 *************************************************************************/
86 .globl tlbtabB
87tlbtabB:
88 tlbtab_start
Stefan Roese2721a682007-03-08 10:07:18 +0100[diff] [blame]89
90 /*
91 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
92 * speed up boot process. It is patched after relocation to enable SA_I
93 */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]94 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]95
96 /*
97 * TLB entries for SDRAM are not needed on this platform.
98 * They are dynamically generated in the SPD DDR(2) detection
99 * routine.
100 */
101
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]102 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]103
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]104 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]105
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]106 tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]107
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]108 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
109 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
110 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]111
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]112 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
113 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
114 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
115 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
116 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
117 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]118 tlbtab_end