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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8240 1
40#define CONFIG_OXC 1
41
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenkc6097192002-11-03 00:24:07 +000043
44#define CONFIG_IDENT_STRING " [oxc] "
45
46#define CONFIG_WATCHDOG 1
47#define CONFIG_SHOW_ACTIVITY 1
48#define CONFIG_SHOW_BOOT_PROGRESS 1
49
50#define CONFIG_CONS_INDEX 1
51#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkc6097192002-11-03 00:24:07 +000053
wdenkc6097192002-11-03 00:24:07 +000054
Jon Loeligere18a1062007-07-08 14:21:43 -050055/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050056 * BOOTP options
57 */
58#define CONFIG_BOOTP_BOOTFILESIZE
59#define CONFIG_BOOTP_BOOTPATH
60#define CONFIG_BOOTP_GATEWAY
61#define CONFIG_BOOTP_HOSTNAME
62
63
64/*
Jon Loeligere18a1062007-07-08 14:21:43 -050065 * Command line configuration.
66 */
67#include <config_cmd_default.h>
68
69#define CONFIG_CMD_ELF
70
wdenkc6097192002-11-03 00:24:07 +000071
72/*
73 * Miscellaneous configurable options
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
76#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
77#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
78#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
79#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
80#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
81#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
82#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +000083
84#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
85
86/*-----------------------------------------------------------------------
87 * Boot options
88 */
89
90#define CONFIG_SERVERIP 10.0.0.1
91#define CONFIG_GATEWAYIP 10.0.0.1
92#define CONFIG_NETMASK 255.255.255.0
93#define CONFIG_LOADADDR 0x10000
94#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf"
95#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000"
96#define CONFIG_BOOTDELAY 10
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_OXC_GENERATE_IP 1 /* Generate IP automatically */
99#define CONFIG_SYS_OXC_IPMASK 0x0A000000 /* 10.0.0.x */
wdenkc6097192002-11-03 00:24:07 +0000100
101/*-----------------------------------------------------------------------
102 * PCI stuff
103 */
104
105#define CONFIG_PCI /* include pci support */
106
107#define CONFIG_NET_MULTI /* Multi ethernet cards support */
108
109#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +0000111
112#define PCI_ENET0_IOADDR 0x80000000
113#define PCI_ENET0_MEMADDR 0x80000000
114#define PCI_ENET1_IOADDR 0x81000000
115#define PCI_ENET1_MEMADDR 0x81000000
116
117/*-----------------------------------------------------------------------
118 * FLASH
119 */
120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH_PRELIMBASE 0xFF800000
122#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size)
wdenkc6097192002-11-03 00:24:07 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
125#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
128#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000129
130/*-----------------------------------------------------------------------
131 * RAM
132 */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_SDRAM_BASE 0x00000000
135#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
140#define CONFIG_SYS_MONITOR_LEN 0x00030000
wdenkc6097192002-11-03 00:24:07 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_PRELIMBASE)
143# define CONFIG_SYS_RAMBOOT 1
wdenkc6097192002-11-03 00:24:07 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145# undef CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000146#endif
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
149#define CONFIG_SYS_INIT_RAM_END 0x1000
wdenkc6097192002-11-03 00:24:07 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_GBL_DATA_SIZE 128
152#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
153#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
158#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000159
160/*-----------------------------------------------------------------------
161 * Memory mapping
162 */
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CPLD_BASE 0xff000000 /* CPLD registers */
165#define CONFIG_SYS_CPLD_WATCHDOG (CONFIG_SYS_CPLD_BASE) /* Watchdog */
166#define CONFIG_SYS_CPLD_RESET (CONFIG_SYS_CPLD_BASE + 0x040000) /* Minor resets */
167#define CONFIG_SYS_UART_BASE (CONFIG_SYS_CPLD_BASE + 0x700000) /* debug UART */
wdenkc6097192002-11-03 00:24:07 +0000168
169/*-----------------------------------------------------------------------
170 * NS16550 Configuration
171 */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_NS16550
174#define CONFIG_SYS_NS16550_SERIAL
175#define CONFIG_SYS_NS16550_REG_SIZE -4
176#define CONFIG_SYS_NS16550_CLK 1843200
177#define CONFIG_SYS_NS16550_COM1 CONFIG_SYS_UART_BASE
wdenkc6097192002-11-03 00:24:07 +0000178
179/*-----------------------------------------------------------------------
180 * I2C Bus
181 */
182
183#define CONFIG_I2C 1 /* I2C support on ... */
184#define CONFIG_HARD_I2C 1 /* ... hardware one */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
186#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
wdenkc6097192002-11-03 00:24:07 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */
189#define CONFIG_SYS_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */
190#define CONFIG_SYS_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */
wdenkc6097192002-11-03 00:24:07 +0000191
192/*-----------------------------------------------------------------------
193 * Environment
194 */
195
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200196#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200197#define CONFIG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */
198#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000199#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */
200
201/*
202 * Low Level Configuration Settings
203 * (address mappings, register initial values, etc.)
204 * You should know what you are doing if you make changes here.
205 */
206
207#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
208#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkc6097192002-11-03 00:24:07 +0000211
212/* MCCR1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_ROMNAL 0 /* rom/flash next access time */
214#define CONFIG_SYS_ROMFAL 19 /* rom/flash access time */
wdenkc6097192002-11-03 00:24:07 +0000215
216/* MCCR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_ASRISE 15 /* ASRISE=15 clocks */
218#define CONFIG_SYS_ASFALL 3 /* ASFALL=3 clocks */
219#define CONFIG_SYS_REFINT 1000 /* REFINT=1000 clocks */
wdenkc6097192002-11-03 00:24:07 +0000220
221/* MCCR3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BSTOPRE 0x35c /* Burst To Precharge */
223#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval */
224#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
wdenkc6097192002-11-03 00:24:07 +0000225
226/* MCCR4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
228#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
229#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
230#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
231#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
232#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */
233#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenkc6097192002-11-03 00:24:07 +0000234
235/* memory bank settings*/
236/*
237 * only bits 20-29 are actually used from these vales to set the
238 * start/end address the upper two bits will be 0, and the lower 20
239 * bits will be set to 0x00000 for a start address, or 0xfffff for an
240 * end address
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_BANK0_START 0x00000000
243#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
244#define CONFIG_SYS_BANK0_ENABLE 1
245#define CONFIG_SYS_BANK1_START 0x00000000
246#define CONFIG_SYS_BANK1_END 0x00000000
247#define CONFIG_SYS_BANK1_ENABLE 0
248#define CONFIG_SYS_BANK2_START 0x00000000
249#define CONFIG_SYS_BANK2_END 0x00000000
250#define CONFIG_SYS_BANK2_ENABLE 0
251#define CONFIG_SYS_BANK3_START 0x00000000
252#define CONFIG_SYS_BANK3_END 0x00000000
253#define CONFIG_SYS_BANK3_ENABLE 0
254#define CONFIG_SYS_BANK4_START 0x00000000
255#define CONFIG_SYS_BANK4_END 0x00000000
256#define CONFIG_SYS_BANK4_ENABLE 0
257#define CONFIG_SYS_BANK5_START 0x00000000
258#define CONFIG_SYS_BANK5_END 0x00000000
259#define CONFIG_SYS_BANK5_ENABLE 0
260#define CONFIG_SYS_BANK6_START 0x00000000
261#define CONFIG_SYS_BANK6_END 0x00000000
262#define CONFIG_SYS_BANK6_ENABLE 0
263#define CONFIG_SYS_BANK7_START 0x00000000
264#define CONFIG_SYS_BANK7_END 0x00000000
265#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000266/*
267 * Memory bank enable bitmask, specifying which of the banks defined above
268 are actually present. MSB is for bank #7, LSB is for bank #0.
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_BANK_ENABLE 0x01
wdenkc6097192002-11-03 00:24:07 +0000271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
wdenkc6097192002-11-03 00:24:07 +0000273 /* see 8240 book for bit definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenkc6097192002-11-03 00:24:07 +0000275 /* currently accessed page in memory */
276 /* see 8240 book for details */
277
278/* SDRAM 0 - 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
280#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000281
282/* stack in DCACHE @ 1GB (no backing mem) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
284#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000285
286/* PCI memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
288#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000289
290/* Flash, config addrs, etc */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
292#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
295#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
296#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
297#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
298#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
299#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
300#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
301#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000302
303/*
304 * For booting Linux, the board info and command line data
305 * have to be in the first 8 MB of memory, since this is
306 * the maximum mapped by the Linux kernel during initialization.
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000309
310/*-----------------------------------------------------------------------
311 * Cache Configuration
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligere18a1062007-07-08 14:21:43 -0500314#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000316#endif
317
318/*
319 * Internal Definitions
320 *
321 * Boot Flags
322 */
323#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
324#define BOOTFLAG_WARM 0x02 /* Software reboot */
325
326#endif /* __CONFIG_H */