blob: 56d24f90140b3e6f7c988afdae52856b347653f4 [file] [log] [blame]
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 *
4 * (C) Copyright 2010
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25/*
26 * ve8313 board configuration file
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_E300 1
36#define CONFIG_MPC83xx 1
37#define CONFIG_MPC831x 1
38#define CONFIG_MPC8313 1
39#define CONFIG_VE8313 1
40
41#define CONFIG_PCI 1
Kumar Galaa2243b82010-08-19 01:48:14 -050042#define CONFIG_FSL_ELBC 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020043
44#define CONFIG_BOARD_EARLY_INIT_F 1
45
46/*
47 * On-board devices
48 *
49 */
50#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
51
52#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
53
54#define CONFIG_SYS_IMMR 0xE0000000
55
56#define CONFIG_SYS_MEMTEST_START 0x00001000
57#define CONFIG_SYS_MEMTEST_END 0x07000000
58
59#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
60#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
61
62/*
63 * Device configurations
64 */
65
66/*
67 * DDR Setup
68 */
69#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
70#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
71#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
72
73/*
74 * Manually set up DDR parameters, as this board does not
75 * have the SPD connected to I2C.
76 */
77#define CONFIG_SYS_DDR_SIZE 128 /* MB */
78#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
79 | CSCONFIG_AP \
80 | 0x00040000 /* TODO */ \
81 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
82 /* 0x80840102 */
83
84#define CONFIG_SYS_DDR_TIMING_3 0x00000000
85#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
86 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
87 | ( 3 << TIMING_CFG0_RRT_SHIFT ) \
88 | ( 2 << TIMING_CFG0_WWT_SHIFT ) \
89 | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
90 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
91 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
92 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
93 /* 0x0e720802 */
94#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
95 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
96 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
97 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
98 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
99 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
100 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
101 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
102 /* 0x26256222 */
103#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
104 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
105 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
106 | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
107 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
108 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
109 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
110 /* 0x029028c7 */
111#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
112 | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
113 /* 0x03202000 */
114#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
115 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
116 | SDRAM_CFG_32_BE )
117 /* 0x43080000 */
118#define CONFIG_SYS_SDRAM_CFG2 0x00401000
119#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
120 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
121 /* 0x44400232 */
122#define CONFIG_SYS_DDR_MODE_2 0x8000C000
123
124#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
125 /*0x02000000*/
126#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
127 | DDRCDR_PZ_NOMZ \
128 | DDRCDR_NZ_NOMZ \
129 | DDRCDR_M_ODR )
130 /* 0x73000002 */
131
132/*
133 * FLASH on the Local Bus
134 */
135#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
136#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
137#define CONFIG_SYS_FLASH_BASE 0xFE000000
138#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
139#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
140#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
141
142#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \
143 (2 << BR_PS_SHIFT) | /* 16 bit */ \
144 BR_V) /* valid */
145#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
146 | OR_GPCM_CSNT \
147 | OR_GPCM_ACS_DIV4 \
148 | OR_GPCM_SCY_5 \
149 | OR_GPCM_TRLX \
150 | OR_GPCM_EAD)
151 /* 0xfe000c55 */
152
153#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
154#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
155
156#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
157#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
158
159#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
160#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
161
162#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
163
164#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
165#define CONFIG_SYS_RAMBOOT
166#endif
167
168#define CONFIG_SYS_INIT_RAM_LOCK 1
169#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
170#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
171
172#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
174 CONFIG_SYS_GBL_DATA_SIZE)
175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176
177/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
178#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
179#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
180
181/*
182 * Local Bus LCRR and LBCR regs
183 */
184#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
185#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
186
187#define CONFIG_SYS_LBC_LBCR 0x00040000
188
189#define CONFIG_SYS_LBC_MRTPR 0x20000000
190
191/*
192 * NAND settings
193 */
194#define CONFIG_SYS_NAND_BASE 0x61000000
195#define CONFIG_SYS_MAX_NAND_DEVICE 1
196#define CONFIG_MTD_NAND_VERIFY_WRITE
197#define CONFIG_CMD_NAND 1
198#define CONFIG_NAND_FSL_ELBC 1
199#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
200
201#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
202 | BR_PS_8 \
203 | BR_DECC_CHK_GEN \
204 | BR_MS_FCM \
205 | BR_V ) /* valid */
206 /* 0x61000c21 */
207#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
208 | OR_FCM_BCTLD \
209 | OR_FCM_CHT \
210 | OR_FCM_SCY_2 \
211 | OR_FCM_RST \
212 | OR_FCM_TRLX)
213 /* 0xffff90ac */
214
215#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
216#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
217#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
218#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
219
220#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
221#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
222
223#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
224#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
225
226/* CS2 NvRAM */
227#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
228 | BR_PS_8 \
229 | BR_V)
230 /* 0x60000801 */
231#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
232 | OR_GPCM_CSNT \
233 | OR_GPCM_XACS \
234 | OR_GPCM_SCY_3 \
235 | OR_GPCM_TRLX \
236 | OR_GPCM_EHTR \
237 | OR_GPCM_EAD)
238 /* 0xfffe0937 */
239/* local bus read write buffer mapping SRAM@0x64000000 */
240#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
241 | BR_PS_16 \
242 | BR_V)
243 /* 0x62001001 */
244
245#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
246 | OR_GPCM_CSNT \
247 | OR_GPCM_XACS \
248 | OR_GPCM_SCY_15 \
249 | OR_GPCM_TRLX \
250 | OR_GPCM_EHTR \
251 | OR_GPCM_EAD)
252 /* 0xfe0009f7 */
253
254/* pass open firmware flat tree */
255#define CONFIG_OF_LIBFDT 1
256#define CONFIG_OF_BOARD_SETUP 1
257#define CONFIG_OF_STDOUT_VIA_ALIAS 1
258
259/*
260 * Serial Port
261 */
262#define CONFIG_CONS_INDEX 1
263#define CONFIG_SYS_NS16550
264#define CONFIG_SYS_NS16550_SERIAL
265#define CONFIG_SYS_NS16550_REG_SIZE 1
266#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
267
268#define CONFIG_SYS_BAUDRATE_TABLE \
269 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
270
271#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
272#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
273
274/* Use the HUSH parser */
275#define CONFIG_SYS_HUSH_PARSER
276#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
277
278#if defined(CONFIG_PCI)
279/*
280 * General PCI
281 * Addresses are mapped 1-1.
282 */
283#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
284#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
285#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
286#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
287#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
288#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
289#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
290#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
291#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
292
293#define CONFIG_PCI_PNP /* do pci plug-and-play */
294#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
295#endif
296
297/*
298 * TSEC
299 */
300#define CONFIG_TSEC_ENET /* TSEC ethernet support */
301
302#define CONFIG_NET_MULTI
303
304#define CONFIG_TSEC1
305#ifdef CONFIG_TSEC1
306#define CONFIG_HAS_ETH0
307#define CONFIG_TSEC1_NAME "TSEC1"
308#define CONFIG_SYS_TSEC1_OFFSET 0x24000
309#define TSEC1_PHY_ADDR 0x01
310#define TSEC1_FLAGS 0
311#define TSEC1_PHYIDX 0
312#endif
313
314/* Options are: TSEC[0-1] */
315#define CONFIG_ETHPRIME "TSEC1"
316
317/*
318 * Environment
319 */
320#define CONFIG_ENV_IS_IN_FLASH 1
321#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
322 CONFIG_SYS_MONITOR_LEN)
323#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
324#define CONFIG_ENV_SIZE 0x4000
325/* Address and size of Redundant Environment Sector */
326#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
327 CONFIG_ENV_SECT_SIZE)
328#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
329
330#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
331#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
332
333/*
334 * BOOTP options
335 */
336#define CONFIG_BOOTP_BOOTFILESIZE
337#define CONFIG_BOOTP_BOOTPATH
338#define CONFIG_BOOTP_GATEWAY
339#define CONFIG_BOOTP_HOSTNAME
340
341/*
342 * Command line configuration.
343 */
344#include <config_cmd_default.h>
345
346#define CONFIG_CMD_DHCP
347#define CONFIG_CMD_MII
348#define CONFIG_CMD_PING
349#define CONFIG_CMD_PCI
350
351#define CONFIG_CMDLINE_EDITING 1
352#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
353
354/*
355 * Miscellaneous configurable options
356 */
357#define CONFIG_SYS_LONGHELP /* undef to save memory */
358#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
359#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
360#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
361
362#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
363#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
364#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
365#define CONFIG_SYS_HZ 1000 /* 1ms ticks */
366
367/*
368 * For booting Linux, the board info and command line data
369 * have to be in the first 8 MB of memory, since this is
370 * the maximum mapped by the Linux kernel during initialization.
371 */
372#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
373
374/* 0x64050000 */
375#define CONFIG_SYS_HRCW_LOW (\
376 0x20000000 /* reserved, must be set */ |\
377 HRCWL_DDRCM |\
378 HRCWL_CSB_TO_CLKIN_4X1 | \
379 HRCWL_CORE_TO_CSB_2_5X1)
380
381/* 0xa0600004 */
382#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
383 HRCWH_PCI_ARBITER_ENABLE | \
384 HRCWH_CORE_ENABLE | \
385 HRCWH_FROM_0X00000100 | \
386 HRCWH_BOOTSEQ_DISABLE |\
387 HRCWH_SW_WATCHDOG_DISABLE |\
388 HRCWH_ROM_LOC_LOCAL_16BIT | \
389 HRCWH_TSEC1M_IN_MII | \
390 HRCWH_BIG_ENDIAN | \
391 HRCWH_LALE_EARLY)
392
393/* System IO Config */
394#define CONFIG_SYS_SICRH (0x01000000 | \
395 SICRH_ETSEC2_B | \
396 SICRH_ETSEC2_C | \
397 SICRH_ETSEC2_D | \
398 SICRH_ETSEC2_E | \
399 SICRH_ETSEC2_F | \
400 SICRH_ETSEC2_G | \
401 SICRH_TSOBI1 | \
402 SICRH_TSOBI2)
403 /* 0x010fff03 */
404#define CONFIG_SYS_SICRL (SICRL_LBC | \
405 SICRL_SPI_A | \
406 SICRL_SPI_B | \
407 SICRL_SPI_C | \
408 SICRL_SPI_D | \
409 SICRL_ETSEC2_A)
410 /* 0x33fc0003) */
411
412#define CONFIG_SYS_HID0_INIT 0x000000000
413#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
414 HID0_ENABLE_INSTRUCTION_CACHE)
415
416#define CONFIG_SYS_HID2 HID2_HBE
417
418#define CONFIG_HIGH_BATS 1 /* High BATs supported */
419
420/* DDR @ 0x00000000 */
421#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
422#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
423 BATU_VS | BATU_VP)
424
425#if defined(CONFIG_PCI)
426/* PCI @ 0x80000000 */
427#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
428#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
429 BATU_VS | BATU_VP)
430#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
431 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
432#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
433 BATU_VS | BATU_VP)
434#else
435#define CONFIG_SYS_IBAT1L (0)
436#define CONFIG_SYS_IBAT1U (0)
437#define CONFIG_SYS_IBAT2L (0)
438#define CONFIG_SYS_IBAT2U (0)
439#endif
440
441/* PCI2 not supported on 8313 */
442#define CONFIG_SYS_IBAT3L (0)
443#define CONFIG_SYS_IBAT3U (0)
444#define CONFIG_SYS_IBAT4L (0)
445#define CONFIG_SYS_IBAT4U (0)
446
447/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
448#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
449 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
450#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
451 BATU_VP)
452
453/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
454#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
455#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
456
457/* FPGA, SRAM, NAND @ 0x60000000 */
458#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
459#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
460
461#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
462#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
463#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
464#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
465#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
466#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
467#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
468#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
469#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
470#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
471#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
472#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
473#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
474#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
475#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
476#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
477
478/*
479 * Internal Definitions
480 *
481 * Boot Flags
482 */
483#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
484#define BOOTFLAG_WARM 0x02 /* Software reboot */
485
486#define CONFIG_NETDEV eth0
487
488#define CONFIG_HOSTNAME ve8313
489#define CONFIG_UBOOTPATH ve8313/u-boot.bin
490
491#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
492#define CONFIG_BAUDRATE 115200
493
494#define XMK_STR(x) #x
495#define MK_STR(x) XMK_STR(x)
496
497#define CONFIG_EXTRA_ENV_SETTINGS \
498 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
499 "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
500 "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
501 "u-boot_addr_r=100000\0" \
502 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
503 "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
504 "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
505 "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
506 " ${filesize};" \
507 "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
508
509#undef MK_STR
510#undef XMK_STR
511
512#endif /* __CONFIG_H */