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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/* U-Boot - Startup Code for PowerPC based Embedded Boards
26 *
27 *
28 * The processor starts at 0x00000100 and the code is executed
29 * from flash. The code is organized to be at an other address
30 * in memory, but as long we don't jump around before relocating.
31 * board_init lies at a quite high address and when the cpu has
32 * jumped there, everything is ok.
33 * This works because the cpu gives the FLASH (CS0) the whole
34 * address space at startup, and board_init lies as a echo of
35 * the flash somewhere up there in the memorymap.
36 *
37 * board_init will change CS0 to be positioned at the correct
38 * address and (s)dram will be positioned at address 0
39 */
40#include <config.h>
41#include <mpc824x.h>
Peter Tyser561858e2008-11-03 09:30:59 -060042#include <timestamp.h>
wdenkc6097192002-11-03 00:24:07 +000043#include <version.h>
44
45#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
46
47#include <ppc_asm.tmpl>
48#include <ppc_defs.h>
49
50#include <asm/cache.h>
51#include <asm/mmu.h>
52
53#ifndef CONFIG_IDENT_STRING
54#define CONFIG_IDENT_STRING ""
55#endif
56
57/* We don't want the MMU yet.
58*/
59#undef MSR_KERNEL
60/* FP, Machine Check and Recoverable Interr. */
61#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
62
63/*
64 * Set up GOT: Global Offset Table
65 *
66 * Use r14 to access the GOT
67 */
68 START_GOT
69 GOT_ENTRY(_GOT2_TABLE_)
70 GOT_ENTRY(_FIXUP_TABLE_)
71
72 GOT_ENTRY(_start)
73 GOT_ENTRY(_start_of_vectors)
74 GOT_ENTRY(_end_of_vectors)
75 GOT_ENTRY(transfer_to_handler)
76
wdenk3b57fe02003-05-30 12:48:29 +000077 GOT_ENTRY(__init_end)
wdenkc6097192002-11-03 00:24:07 +000078 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +000079 GOT_ENTRY(__bss_start)
wdenkc6097192002-11-03 00:24:07 +000080#if defined(CONFIG_FADS)
81 GOT_ENTRY(environment)
82#endif
83 END_GOT
84
85/*
86 * r3 - 1st arg to board_init(): IMMP pointer
87 * r4 - 2nd arg to board_init(): boot flag
88 */
89 .text
90 .long 0x27051956 /* U-Boot Magic Number */
91 .globl version_string
92version_string:
93 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -060094 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenkc6097192002-11-03 00:24:07 +000095 .ascii CONFIG_IDENT_STRING, "\0"
96
97 . = EXC_OFF_SYS_RESET
98 .globl _start
99_start:
100 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
101 b boot_cold
102
103 . = EXC_OFF_SYS_RESET + 0x10
104
105 .globl _start_warm
106_start_warm:
107 li r21, BOOTFLAG_WARM /* Software reboot */
108 b boot_warm
109
110boot_cold:
111boot_warm:
112
113 /* Initialize machine status; enable machine check interrupt */
114 /*----------------------------------------------------------------------*/
115 li r3, MSR_KERNEL /* Set FP, ME, RI flags */
116 mtmsr r3
117 mtspr SRR1, r3 /* Make SRR1 match MSR */
118
119 addis r0,0,0x0000 /* lets make sure that r0 is really 0 */
120 mtspr HID0, r0 /* disable I and D caches */
121
122 mfspr r3, ICR /* clear Interrupt Cause Register */
123
124 mfmsr r3 /* turn off address translation */
125 addis r4,0,0xffff
126 ori r4,r4,0xffcf
127 and r3,r3,r4
128 mtmsr r3
129 isync
130 sync /* the MMU should be off... */
131
132
133in_flash:
134#if defined(CONFIG_BMW)
135 bl early_init_f /* Must be ASM: no stack yet! */
136#endif
137 /*
138 * Setup BATs - cannot be done in C since we don't have a stack yet
139 */
140 bl setup_bats
141
142 /* Enable MMU.
143 */
144 mfmsr r3
145 ori r3, r3, (MSR_IR | MSR_DR)
146 mtmsr r3
147#if !defined(CONFIG_BMW)
148 /* Enable and invalidate data cache.
149 */
150 mfspr r3, HID0
151 mr r2, r3
152 ori r3, r3, HID0_DCE | HID0_DCI
153 ori r2, r2, HID0_DCE
154 sync
155 mtspr HID0, r3
156 mtspr HID0, r2
157 sync
158
159 /* Allocate Initial RAM in data cache.
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
162 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
wdenkc6097192002-11-03 00:24:07 +0000163 li r2, 128
164 mtctr r2
1651:
166 dcbz r0, r3
167 addi r3, r3, 32
168 bdnz 1b
169
170 /* Lock way0 in data cache.
171 */
172 mfspr r3, 1011
173 lis r2, 0xffff
174 ori r2, r2, 0xff1f
175 and r3, r3, r2
176 ori r3, r3, 0x0080
177 sync
178 mtspr 1011, r3
179#endif /* !CONFIG_BMW */
180 /*
181 * Thisk the stack pointer *somewhere* sensible. Doesnt
182 * matter much where as we'll move it when we relocate
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
185 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
wdenkc6097192002-11-03 00:24:07 +0000186
187 li r0, 0 /* Make room for stack frame header and */
188 stwu r0, -4(r1) /* clear final stack frame so that */
189 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
190
191 /* let the C-code set up the rest */
192 /* */
193 /* Be careful to keep code relocatable ! */
194 /*----------------------------------------------------------------------*/
195
196 GET_GOT /* initialize GOT access */
197
198 /* r3: IMMR */
199 bl cpu_init_f /* run low-level CPU init code (from Flash) */
200
201 mr r3, r21
202 /* r3: BOOTFLAG */
203 bl board_init_f /* run 1st part of board init code (from Flash) */
204
205
wdenkc6097192002-11-03 00:24:07 +0000206 .globl _start_of_vectors
207_start_of_vectors:
208
209/* Machine check */
210 STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
211
212/* Data Storage exception. "Never" generated on the 860. */
213 STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
214
215/* Instruction Storage exception. "Never" generated on the 860. */
216 STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
217
218/* External Interrupt exception. */
219 STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
220
221/* Alignment exception. */
222 . = EXC_OFF_ALIGN
223Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200224 EXCEPTION_PROLOG(SRR0, SRR1)
wdenkc6097192002-11-03 00:24:07 +0000225 mfspr r4,DAR
226 stw r4,_DAR(r21)
227 mfspr r5,DSISR
228 stw r5,_DSISR(r21)
229 addi r3,r1,STACK_FRAME_OVERHEAD
230 li r20,MSR_KERNEL
231 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
232 lwz r6,GOT(transfer_to_handler)
233 mtlr r6
234 blrl
235.L_Alignment:
236 .long AlignmentException - _start + EXC_OFF_SYS_RESET
237 .long int_return - _start + EXC_OFF_SYS_RESET
238
239/* Program check exception */
240 . = EXC_OFF_PROGRAM
241ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200242 EXCEPTION_PROLOG(SRR0, SRR1)
wdenkc6097192002-11-03 00:24:07 +0000243 addi r3,r1,STACK_FRAME_OVERHEAD
244 li r20,MSR_KERNEL
245 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
246 lwz r6,GOT(transfer_to_handler)
247 mtlr r6
248 blrl
249.L_ProgramCheck:
250 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
251 .long int_return - _start + EXC_OFF_SYS_RESET
252
253 /* No FPU on MPC8xx. This exception is not supposed to happen.
254 */
255 STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
256
257 /* I guess we could implement decrementer, and may have
258 * to someday for timekeeping.
259 */
260 STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
261 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
262 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000263 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenkc6097192002-11-03 00:24:07 +0000264
265 STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
266
267 STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
268 STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
269
270 STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
271 STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
272 STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
wdenk43d96162003-03-06 00:02:04 +0000273 STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
wdenkc6097192002-11-03 00:24:07 +0000274 STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
275 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
276 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
277 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
278 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
279 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
280 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
281 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
282 STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
283 STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
284 STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
285 STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
286
287 STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
288
289 .globl _end_of_vectors
290_end_of_vectors:
291
292
293 . = 0x3000
294
295/*
296 * This code finishes saving the registers to the exception frame
297 * and jumps to the appropriate handler for the exception.
298 * Register r21 is pointer into trap frame, r1 has new stack pointer.
299 */
300 .globl transfer_to_handler
301transfer_to_handler:
302 stw r22,_NIP(r21)
303 lis r22,MSR_POW@h
304 andc r23,r23,r22
305 stw r23,_MSR(r21)
306 SAVE_GPR(7, r21)
307 SAVE_4GPRS(8, r21)
308 SAVE_8GPRS(12, r21)
309 SAVE_8GPRS(24, r21)
310#if 0
311 andi. r23,r23,MSR_PR
312 mfspr r23,SPRG3 /* if from user, fix up tss.regs */
313 beq 2f
314 addi r24,r1,STACK_FRAME_OVERHEAD
315 stw r24,PT_REGS(r23)
3162: addi r2,r23,-TSS /* set r2 to current */
317 tovirt(r2,r2,r23)
318#endif
319 mflr r23
320 andi. r24,r23,0x3f00 /* get vector offset */
321 stw r24,TRAP(r21)
322 li r22,0
323 stw r22,RESULT(r21)
324 mtspr SPRG2,r22 /* r1 is now kernel sp */
325#if 0
326 addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
327 cmplw 0,r1,r2
328 cmplw 1,r1,r24
329 crand 1,1,4
330 bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
331#endif
332 lwz r24,0(r23) /* virtual address of handler */
333 lwz r23,4(r23) /* where to go when done */
334 mtspr SRR0,r24
335 ori r20,r20,0x30 /* enable IR, DR */
336 mtspr SRR1,r20
337 mtlr r23
338 SYNC
339 rfi /* jump to handler, enable MMU */
340
341int_return:
342 mfmsr r28 /* Disable interrupts */
343 li r4,0
344 ori r4,r4,MSR_EE
345 andc r28,r28,r4
346 SYNC /* Some chip revs need this... */
347 mtmsr r28
348 SYNC
349 lwz r2,_CTR(r1)
350 lwz r0,_LINK(r1)
351 mtctr r2
352 mtlr r0
353 lwz r2,_XER(r1)
354 lwz r0,_CCR(r1)
355 mtspr XER,r2
356 mtcrf 0xFF,r0
357 REST_10GPRS(3, r1)
358 REST_10GPRS(13, r1)
359 REST_8GPRS(23, r1)
360 REST_GPR(31, r1)
361 lwz r2,_NIP(r1) /* Restore environment */
362 lwz r0,_MSR(r1)
363 mtspr SRR0,r2
364 mtspr SRR1,r0
365 lwz r0,GPR0(r1)
366 lwz r2,GPR2(r1)
367 lwz r1,GPR1(r1)
368 SYNC
369 rfi
370
371/* Cache functions.
372*/
373 .globl icache_enable
374icache_enable:
375 mfspr r5,HID0 /* turn on the I cache. */
376 ori r5,r5,0x8800 /* Instruction cache only! */
377 addis r6,0,0xFFFF
378 ori r6,r6,0xF7FF
379 and r6,r5,r6 /* clear the invalidate bit */
380 sync
381 mtspr HID0,r5
382 mtspr HID0,r6
383 isync
384 sync
385 blr
386
387 .globl icache_disable
388icache_disable:
389 mfspr r5,HID0
390 addis r6,0,0xFFFF
391 ori r6,r6,0x7FFF
392 and r5,r5,r6
393 sync
394 mtspr HID0,r5
395 isync
396 sync
397 blr
398
399 .globl icache_status
400icache_status:
401 mfspr r3, HID0
402 srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */
403 andi. r3, r3, 1
404 blr
405
406 .globl dcache_enable
407dcache_enable:
408 mfspr r5,HID0 /* turn on the D cache. */
409 ori r5,r5,0x4400 /* Data cache only! */
410 mfspr r4, PVR /* read PVR */
411 srawi r3, r4, 16 /* shift off the least 16 bits */
412 cmpi 0, 0, r3, 0xC /* Check for Max pvr */
413 bne NotMax
414 ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */
415NotMax:
416 addis r6,0,0xFFFF
417 ori r6,r6,0xFBFF
418 and r6,r5,r6 /* clear the invalidate bit */
419 sync
420 mtspr HID0,r5
421 mtspr HID0,r6
422 isync
423 sync
424 blr
425
426 .globl dcache_disable
427dcache_disable:
428 mfspr r5,HID0
429 addis r6,0,0xFFFF
430 ori r6,r6,0xBFFF
431 and r5,r5,r6
432 sync
433 mtspr HID0,r5
434 isync
435 sync
436 blr
437
438 .globl dcache_status
439dcache_status:
440 mfspr r3, HID0
441 srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */
442 andi. r3, r3, 1
443 blr
444
445 .globl dc_read
446dc_read:
447/*TODO : who uses this, what should it do?
448*/
449 blr
450
451
452 .globl get_pvr
453get_pvr:
454 mfspr r3, PVR
455 blr
456
457
458/*------------------------------------------------------------------------------*/
459
460/*
461 * void relocate_code (addr_sp, gd, addr_moni)
462 *
463 * This "function" does not return, instead it continues in RAM
464 * after relocating the monitor code.
465 *
466 * r3 = dest
467 * r4 = src
468 * r5 = length in bytes
469 * r6 = cachelinesize
470 */
471 .globl relocate_code
472relocate_code:
473
474 mr r1, r3 /* Set new stack pointer */
475 mr r9, r4 /* Save copy of Global Data pointer */
476 mr r10, r5 /* Save copy of Destination Address */
477
478 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#ifdef CONFIG_SYS_RAMBOOT
480 lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */
481 ori r4, r4, CONFIG_SYS_SDRAM_BASE@l
wdenkc6097192002-11-03 00:24:07 +0000482#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
484 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenkc6097192002-11-03 00:24:07 +0000485#endif
wdenk3b57fe02003-05-30 12:48:29 +0000486 lwz r5, GOT(__init_end)
487 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenkc6097192002-11-03 00:24:07 +0000489
490 /*
491 * Fix GOT pointer:
492 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenkc6097192002-11-03 00:24:07 +0000494 *
495 * Offset:
496 */
497 sub r15, r10, r4
498
499 /* First our own GOT */
500 add r14, r14, r15
501 /* the the one used by the C code */
502 add r30, r30, r15
503
504 /*
505 * Now relocate code
506 */
507
508 cmplw cr1,r3,r4
509 addi r0,r5,3
510 srwi. r0,r0,2
511 beq cr1,4f /* In place copy is not necessary */
512 beq 7f /* Protect against 0 count */
513 mtctr r0
514 bge cr1,2f
515
516 la r8,-4(r4)
517 la r7,-4(r3)
5181: lwzu r0,4(r8)
519 stwu r0,4(r7)
520 bdnz 1b
521 b 4f
522
5232: slwi r0,r0,2
524 add r8,r4,r0
525 add r7,r3,r0
5263: lwzu r0,-4(r8)
527 stwu r0,-4(r7)
528 bdnz 3b
529
wdenk7205e402003-09-10 22:30:53 +00005304:
531#if !defined(CONFIG_BMW)
532/* Unlock the data cache and invalidate locked area */
533 xor r0, r0, r0
534 mtspr 1011, r0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535 lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
536 ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
wdenk7205e402003-09-10 22:30:53 +0000537 li r0, 128
538 mtctr r0
53941:
540 dcbi r0, r4
541 addi r4, r4, 32
542 bdnz 41b
543#endif
544
wdenkc6097192002-11-03 00:24:07 +0000545/*
546 * Now flush the cache: note that we must start from a cache aligned
547 * address. Otherwise we might miss one cache line.
548 */
wdenk7205e402003-09-10 22:30:53 +0000549 cmpwi r6,0
wdenkc6097192002-11-03 00:24:07 +0000550 add r5,r3,r5
551 beq 7f /* Always flush prefetch queue in any case */
552 subi r0,r6,1
553 andc r3,r3,r0
554 mr r4,r3
5555: dcbst 0,r4
556 add r4,r4,r6
557 cmplw r4,r5
558 blt 5b
559 sync /* Wait for all dcbst to complete on bus */
560 mr r4,r3
5616: icbi 0,r4
562 add r4,r4,r6
563 cmplw r4,r5
564 blt 6b
5657: sync /* Wait for all icbi to complete on bus */
566 isync
567
568/*
569 * We are done. Do not return, instead branch to second part of board
570 * initialization, now running from RAM.
571 */
572
573 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
574 mtlr r0
575 blr
576
577in_ram:
578
579 /*
580 * Relocation Function, r14 point to got2+0x8000
581 *
582 * Adjust got2 pointers, no need to check for 0, this code
583 * already puts a few entries in the table.
584 */
585 li r0,__got2_entries@sectoff@l
586 la r3,GOT(_GOT2_TABLE_)
587 lwz r11,GOT(_GOT2_TABLE_)
588 mtctr r0
589 sub r11,r3,r11
590 addi r3,r3,-4
5911: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200592 cmpwi r0,0
593 beq- 2f
wdenkc6097192002-11-03 00:24:07 +0000594 add r0,r0,r11
595 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02005962: bdnz 1b
wdenkc6097192002-11-03 00:24:07 +0000597
598 /*
599 * Now adjust the fixups and the pointers to the fixups
600 * in case we need to move ourselves again.
601 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200602 li r0,__fixup_entries@sectoff@l
wdenkc6097192002-11-03 00:24:07 +0000603 lwz r3,GOT(_FIXUP_TABLE_)
604 cmpwi r0,0
605 mtctr r0
606 addi r3,r3,-4
607 beq 4f
6083: lwzu r4,4(r3)
609 lwzux r0,r4,r11
610 add r0,r0,r11
611 stw r10,0(r3)
612 stw r0,0(r4)
613 bdnz 3b
6144:
615clear_bss:
616 /*
617 * Now clear BSS segment
618 */
wdenk5d232d02003-05-22 22:52:13 +0000619 lwz r3,GOT(__bss_start)
wdenkc6097192002-11-03 00:24:07 +0000620 lwz r4,GOT(_end)
621
622 cmplw 0, r3, r4
623 beq 6f
624
625 li r0, 0
6265:
627 stw r0, 0(r3)
628 addi r3, r3, 4
629 cmplw 0, r3, r4
630 blt 5b
6316:
632
633 mr r3, r9 /* Global Data pointer */
634 mr r4, r10 /* Destination Address */
635 bl board_init_r
636
wdenkc6097192002-11-03 00:24:07 +0000637 /*
638 * Copy exception vector code to low memory
639 *
640 * r3: dest_addr
641 * r7: source address, r8: end address, r9: target address
642 */
643 .globl trap_init
644trap_init:
645 lwz r7, GOT(_start)
646 lwz r8, GOT(_end_of_vectors)
647
wdenk682011f2003-06-03 23:54:09 +0000648 li r9, 0x100 /* reset vector always at 0x100 */
wdenkc6097192002-11-03 00:24:07 +0000649
650 cmplw 0, r7, r8
651 bgelr /* return if r7>=r8 - just in case */
652
653 mflr r4 /* save link register */
6541:
655 lwz r0, 0(r7)
656 stw r0, 0(r9)
657 addi r7, r7, 4
658 addi r9, r9, 4
659 cmplw 0, r7, r8
660 bne 1b
661
662 /*
663 * relocate `hdlr' and `int_return' entries
664 */
665 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
666 li r8, Alignment - _start + EXC_OFF_SYS_RESET
6672:
668 bl trap_reloc
669 addi r7, r7, 0x100 /* next exception vector */
670 cmplw 0, r7, r8
671 blt 2b
672
673 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
674 bl trap_reloc
675
676 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
677 bl trap_reloc
678
679 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
680 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
6813:
682 bl trap_reloc
683 addi r7, r7, 0x100 /* next exception vector */
684 cmplw 0, r7, r8
685 blt 3b
686
687 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
688 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6894:
690 bl trap_reloc
691 addi r7, r7, 0x100 /* next exception vector */
692 cmplw 0, r7, r8
693 blt 4b
694
695 mtlr r4 /* restore link register */
696 blr
697
698 /*
699 * Function: relocate entries for one exception vector
700 */
701trap_reloc:
702 lwz r0, 0(r7) /* hdlr ... */
703 add r0, r0, r3 /* ... += dest_addr */
704 stw r0, 0(r7)
705
706 lwz r0, 4(r7) /* int_return ... */
707 add r0, r0, r3 /* ... += dest_addr */
708 stw r0, 4(r7)
709
710 blr
711
712 /* Setup the BAT registers.
713 */
714setup_bats:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200715 lis r4, CONFIG_SYS_IBAT0L@h
716 ori r4, r4, CONFIG_SYS_IBAT0L@l
717 lis r3, CONFIG_SYS_IBAT0U@h
718 ori r3, r3, CONFIG_SYS_IBAT0U@l
wdenkc6097192002-11-03 00:24:07 +0000719 mtspr IBAT0L, r4
720 mtspr IBAT0U, r3
721 isync
722
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200723 lis r4, CONFIG_SYS_DBAT0L@h
724 ori r4, r4, CONFIG_SYS_DBAT0L@l
725 lis r3, CONFIG_SYS_DBAT0U@h
726 ori r3, r3, CONFIG_SYS_DBAT0U@l
wdenkc6097192002-11-03 00:24:07 +0000727 mtspr DBAT0L, r4
728 mtspr DBAT0U, r3
729 isync
730
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200731 lis r4, CONFIG_SYS_IBAT1L@h
732 ori r4, r4, CONFIG_SYS_IBAT1L@l
733 lis r3, CONFIG_SYS_IBAT1U@h
734 ori r3, r3, CONFIG_SYS_IBAT1U@l
wdenkc6097192002-11-03 00:24:07 +0000735 mtspr IBAT1L, r4
736 mtspr IBAT1U, r3
737 isync
738
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200739 lis r4, CONFIG_SYS_DBAT1L@h
740 ori r4, r4, CONFIG_SYS_DBAT1L@l
741 lis r3, CONFIG_SYS_DBAT1U@h
742 ori r3, r3, CONFIG_SYS_DBAT1U@l
wdenkc6097192002-11-03 00:24:07 +0000743 mtspr DBAT1L, r4
744 mtspr DBAT1U, r3
745 isync
746
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200747 lis r4, CONFIG_SYS_IBAT2L@h
748 ori r4, r4, CONFIG_SYS_IBAT2L@l
749 lis r3, CONFIG_SYS_IBAT2U@h
750 ori r3, r3, CONFIG_SYS_IBAT2U@l
wdenkc6097192002-11-03 00:24:07 +0000751 mtspr IBAT2L, r4
752 mtspr IBAT2U, r3
753 isync
754
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200755 lis r4, CONFIG_SYS_DBAT2L@h
756 ori r4, r4, CONFIG_SYS_DBAT2L@l
757 lis r3, CONFIG_SYS_DBAT2U@h
758 ori r3, r3, CONFIG_SYS_DBAT2U@l
wdenkc6097192002-11-03 00:24:07 +0000759 mtspr DBAT2L, r4
760 mtspr DBAT2U, r3
761 isync
762
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200763 lis r4, CONFIG_SYS_IBAT3L@h
764 ori r4, r4, CONFIG_SYS_IBAT3L@l
765 lis r3, CONFIG_SYS_IBAT3U@h
766 ori r3, r3, CONFIG_SYS_IBAT3U@l
wdenkc6097192002-11-03 00:24:07 +0000767 mtspr IBAT3L, r4
768 mtspr IBAT3U, r3
769 isync
770
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200771 lis r4, CONFIG_SYS_DBAT3L@h
772 ori r4, r4, CONFIG_SYS_DBAT3L@l
773 lis r3, CONFIG_SYS_DBAT3U@h
774 ori r3, r3, CONFIG_SYS_DBAT3U@l
wdenkc6097192002-11-03 00:24:07 +0000775 mtspr DBAT3L, r4
776 mtspr DBAT3U, r3
777 isync
778
779 /* Invalidate TLBs.
780 * -> for (val = 0; val < 0x20000; val+=0x1000)
781 * -> tlbie(val);
782 */
783 lis r3, 0
784 lis r5, 2
785
7861:
787 tlbie r3
788 addi r3, r3, 0x1000
789 cmp 0, 0, r3, r5
790 blt 1b
791
792 blr