blob: 2fd8c7b7e3b89a10f3ac6eedc1bd66a35cc4329b [file] [log] [blame]
Patrick Delaunaye70f70a2018-03-12 10:46:11 +01001
2config STM32MP1_DDR
3 bool "STM32MP1 DDR driver"
4 depends on DM && OF_CONTROL && ARCH_STM32MP
5 select RAM
6 select SPL_RAM if SPL
7 default y
8 help
9 activate STM32MP1 DDR controller driver for STM32MP1 soc
10 family: support for LPDDR2, LPDDR3 and DDR3
11 the SDRAM parameters for controleur and phy need to be provided
12 in device tree (computed by DDR tuning tools)
Patrick Delaunay01a75102019-04-10 14:09:27 +020013
14config STM32MP1_DDR_INTERACTIVE
15 bool "STM32MP1 DDR driver : interactive support"
16 depends on STM32MP1_DDR
17 help
18 activate interactive support in STM32MP1 DDR controller driver
19 used for DDR tuning tools
20 to enter in intercative mode type 'd' during SPL DDR driver
21 initialisation
22
23config STM32MP1_DDR_INTERACTIVE_FORCE
24 bool "STM32MP1 DDR driver : force interactive mode"
25 depends on STM32MP1_DDR_INTERACTIVE
26 default n
27 help
28 force interactive mode in STM32MP1 DDR controller driver
29 skip the polling of character 'd' in console
30 useful when SPL is loaded in sysram
31 directly by programmer
Patrick Delaunay0d447522019-04-10 14:09:28 +020032
33config STM32MP1_DDR_TESTS
34 bool "STM32MP1 DDR driver : tests support"
35 depends on STM32MP1_DDR_INTERACTIVE
36 default y
37 help
38 activate test support for interactive support in
39 STM32MP1 DDR controller driver: command test
Patrick Delaunay187c41d2019-04-10 14:09:29 +020040
41config STM32MP1_DDR_TUNING
42 bool "STM32MP1 DDR driver : support of tuning"
43 depends on STM32MP1_DDR_INTERACTIVE
44 default y
45 help
46 activate tuning command in STM32MP1 DDR interactive mode
47 used for DDR tuning tools
48 - DQ Deskew algorithm
49 - DQS Trimming