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wdenkda93ed82004-09-29 11:02:56 +00001/*
Wolfgang Denkcd0402a2010-11-20 15:07:45 +01002 * (C) Copyright 2003-2010
wdenkda93ed82004-09-29 11:02:56 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 * changes for 16M board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#undef CONFIG_MPC860
38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
40#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
41
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xfff00000
43
wdenkda93ed82004-09-29 11:02:56 +000044#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
48#if 0
49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50#else
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52#endif
53
54/* default developmenmt environment */
55
wdenkda93ed82004-09-29 11:02:56 +000056#define CONFIG_ETHADDR 00:0B:17:00:00:00
57
58#define CONFIG_IPADDR 10.10.69.10
59#define CONFIG_SERVERIP 10.10.69.49
60#define CONFIG_NETMASK 255.255.255.0
61#define CONFIG_HOSTNAME QUANTUM
Joe Hershberger8b3637c2011-10-13 13:03:47 +000062#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"
wdenkda93ed82004-09-29 11:02:56 +000063
64#define CONFIG_BOOTARGS "root=/dev/ram rw"
65
66#define CONFIG_BOOTCOMMAND "bootm ff000000"
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "serial#=12345\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenkda93ed82004-09-29 11:02:56 +000071 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
wdenkda93ed82004-09-29 11:02:56 +000073
74/*
75 * Select the more full-featured memory test (Barr embedded systems)
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_ALT_MEMTEST
wdenkda93ed82004-09-29 11:02:56 +000078
79#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkda93ed82004-09-29 11:02:56 +000081
82
83/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
84#define CONFIG_RTC_M48T35A 1
85
86#if 0
87#define CONFIG_WATCHDOG 1 /* watchdog enabled */
88#else
89#undef CONFIG_WATCHDOG
90#endif
91
92/* NVRAM and RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
94#define CONFIG_SYS_NVRAM_SIZE 2048
wdenkda93ed82004-09-29 11:02:56 +000095
96
Jon Loeliger90cc3eb2007-07-04 22:33:23 -050097/*
98 * Command line configuration.
99 */
100#include <config_cmd_default.h>
101
102#define CONFIG_CMD_DATE
103#define CONFIG_CMD_DHCP
104#define CONFIG_CMD_NFS
105#define CONFIG_CMD_PING
106#define CONFIG_CMD_REGINFO
107#define CONFIG_CMD_SNTP
108
wdenkda93ed82004-09-29 11:02:56 +0000109
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500110/*
111 * BOOTP options
112 */
113#define CONFIG_BOOTP_SUBNETMASK
114#define CONFIG_BOOTP_GATEWAY
115#define CONFIG_BOOTP_HOSTNAME
116#define CONFIG_BOOTP_BOOTPATH
117#define CONFIG_BOOTP_BOOTFILESIZE
118
wdenkda93ed82004-09-29 11:02:56 +0000119
wdenkda93ed82004-09-29 11:02:56 +0000120#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200121#define CONFIG_AUTOBOOT_PROMPT \
122 "\nEnter password - autoboot in %d sec...\n", bootdelay
wdenkda93ed82004-09-29 11:02:56 +0000123#define CONFIG_AUTOBOOT_DELAY_STR "system"
124/*
125 * Miscellaneous configurable options
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LONGHELP /* undef to save memory */
128#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500129#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkda93ed82004-09-29 11:02:56 +0000131#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkda93ed82004-09-29 11:02:56 +0000133#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkda93ed82004-09-29 11:02:56 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
wdenkda93ed82004-09-29 11:02:56 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkda93ed82004-09-29 11:02:56 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkda93ed82004-09-29 11:02:56 +0000144
wdenkda93ed82004-09-29 11:02:56 +0000145/*
146 * Low Level Configuration Settings
147 * (address mappings, register initial values, etc.)
148 * You should know what you are doing if you make changes here.
149 */
150/*-----------------------------------------------------------------------
151 * Internal Memory Mapped Register
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_IMMR 0xFA200000
wdenkda93ed82004-09-29 11:02:56 +0000154
155/*-----------------------------------------------------------------------
156 * Definitions for initial stack pointer and data area (in DPRAM)
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200159#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200160#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkda93ed82004-09-29 11:02:56 +0000162
163/*-----------------------------------------------------------------------
164 * Start addresses for the final memory configuration
165 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkda93ed82004-09-29 11:02:56 +0000167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_SDRAM_BASE 0x00000000
169#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenkda93ed82004-09-29 11:02:56 +0000170
171#if 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200172 #define CONFIG_FLASH_CFI_DRIVER
wdenkda93ed82004-09-29 11:02:56 +0000173#else
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200174 #undef CONFIG_FLASH_CFI_DRIVER
wdenkda93ed82004-09-29 11:02:56 +0000175#endif
176
177
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200178#ifdef CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 #define CONFIG_SYS_FLASH_CFI 1
180 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
wdenkda93ed82004-09-29 11:02:56 +0000182#endif
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500185#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenkda93ed82004-09-29 11:02:56 +0000187#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenkda93ed82004-09-29 11:02:56 +0000189#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
191/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
192#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkda93ed82004-09-29 11:02:56 +0000193
194/*
195 * For booting Linux, the board info and command line data
196 * have to be in the first 8 MB of memory, since this is
197 * the maximum mapped by the Linux kernel during initialization.
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkda93ed82004-09-29 11:02:56 +0000200
201/*-----------------------------------------------------------------------
202 * FLASH organization
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
205#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
wdenkda93ed82004-09-29 11:02:56 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
208#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkda93ed82004-09-29 11:02:56 +0000209
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200210#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denkcd0402a2010-11-20 15:07:45 +0100211#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
213#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
wdenkda93ed82004-09-29 11:02:56 +0000215
216/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200217#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
218#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkda93ed82004-09-29 11:02:56 +0000219
220/* FPGA */
221#define CONFIG_MISC_INIT_R
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FPGA_SPARTAN2
223#define CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenkda93ed82004-09-29 11:02:56 +0000224
225
226/*-----------------------------------------------------------------------
227 * Reset address
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
wdenkda93ed82004-09-29 11:02:56 +0000230
231/*-----------------------------------------------------------------------
232 * Cache Configuration
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500235#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkda93ed82004-09-29 11:02:56 +0000237#endif
238
239/*-----------------------------------------------------------------------
240 * SYPCR - System Protection Control 11-9
241 * SYPCR can only be written once after reset!
242 *-----------------------------------------------------------------------
243 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
244 */
245#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkda93ed82004-09-29 11:02:56 +0000247 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
248#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkda93ed82004-09-29 11:02:56 +0000250#endif
251
252/*-----------------------------------------------------------------------
253 * SIUMCR - SIU Module Configuration 11-6
254 *-----------------------------------------------------------------------
255 * PCMCIA config., multi-function pin tri-state
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
wdenkda93ed82004-09-29 11:02:56 +0000258
259/*-----------------------------------------------------------------------
260 * TBSCR - Time Base Status and Control 11-26
261 *-----------------------------------------------------------------------
262 * Clear Reference Interrupt Status, Timebase freezing enabled
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenkda93ed82004-09-29 11:02:56 +0000265
266/*-----------------------------------------------------------------------
267 * RTCSC - Real-Time Clock Status and Control Register 11-27
268 *-----------------------------------------------------------------------
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
271#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
wdenkda93ed82004-09-29 11:02:56 +0000272
273/*-----------------------------------------------------------------------
274 * PISCR - Periodic Interrupt Status and Control 11-31
275 *-----------------------------------------------------------------------
276 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkda93ed82004-09-29 11:02:56 +0000279
280/*-----------------------------------------------------------------------
281 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
282 *-----------------------------------------------------------------------
283 * Reset PLL lock status sticky bit, timer expired status bit and timer
284 * interrupt status bit
285 *
286 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
287 */
288/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
wdenkda93ed82004-09-29 11:02:56 +0000290
291/*-----------------------------------------------------------------------
292 * SCCR - System Clock and reset Control Register 15-27
293 *-----------------------------------------------------------------------
294 * Set clock output, timebase and RTC source and divider,
295 * power management and some other internal clocks
296 */
297#define SCCR_MASK SCCR_EBDF00
298/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
wdenkda93ed82004-09-29 11:02:56 +0000300
301/*-----------------------------------------------------------------------
302 * PCMCIA stuff
303 *-----------------------------------------------------------------------
304 *
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
307#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
308#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
309#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
310#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
311#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
312#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
313#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkda93ed82004-09-29 11:02:56 +0000314
315/*-----------------------------------------------------------------------
316 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
317 *-----------------------------------------------------------------------
318 */
319
320#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
321
322#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
323#undef CONFIG_IDE_LED /* LED for ide not supported */
324#undef CONFIG_IDE_RESET /* reset for ide not supported */
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
327#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkda93ed82004-09-29 11:02:56 +0000328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkda93ed82004-09-29 11:02:56 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkda93ed82004-09-29 11:02:56 +0000332
333/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkda93ed82004-09-29 11:02:56 +0000335
336/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkda93ed82004-09-29 11:02:56 +0000338
339/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkda93ed82004-09-29 11:02:56 +0000341
342/*-----------------------------------------------------------------------
343 *
344 *-----------------------------------------------------------------------
345 *
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347/*#define CONFIG_SYS_DER 0x2002000F*/
348#define CONFIG_SYS_DER 0
wdenkda93ed82004-09-29 11:02:56 +0000349
350/*
351 * Init Memory Controller:
352 *
353 * BR0 and OR0 (FLASH)
354 */
355
356#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
wdenkda93ed82004-09-29 11:02:56 +0000358
359/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
wdenkda93ed82004-09-29 11:02:56 +0000361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
363#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
wdenkda93ed82004-09-29 11:02:56 +0000364
365/*
366 * BR1 and OR1 (SDRAM)
367 *
368 */
369#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
370#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
371
372/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
wdenkda93ed82004-09-29 11:02:56 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
376#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkda93ed82004-09-29 11:02:56 +0000377
378/* RPXLITE mem setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */
380#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
wdenkda93ed82004-09-29 11:02:56 +0000381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
383#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
wdenkda93ed82004-09-29 11:02:56 +0000384
385/*
386 * Memory Periodic Timer Prescaler
387 */
388
389/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_MAMR_PTA 20
wdenkda93ed82004-09-29 11:02:56 +0000391
392/*
393 * Refresh clock Prescalar
394 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
wdenkda93ed82004-09-29 11:02:56 +0000396
397/*
398 * MAMR settings for SDRAM
399 */
400
401/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkda93ed82004-09-29 11:02:56 +0000403 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
404 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
405
406/*
wdenkda93ed82004-09-29 11:02:56 +0000407 * BCSRx
408 *
409 * Board Status and Control Registers
410 *
411 */
412
413#define BCSR0 0xFA400000
414#define BCSR1 0xFA400001
415#define BCSR2 0xFA400002
416#define BCSR3 0xFA400003
417
418#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
419#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
420#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
421#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
422#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
423#define BCSR0_COLTEST 0x20
424#define BCSR0_ETHLPBK 0x40
425#define BCSR0_ETHEN 0x80
426
427#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
428#define BCSR1_PCVCTL6 0x02
429#define BCSR1_PCVCTL5 0x04
430#define BCSR1_PCVCTL4 0x08
431#define BCSR1_IPB5SEL 0x10
432
433#define BCSR2_ENPA5HDR 0x08 /* USB Control */
434#define BCSR2_ENUSBCLK 0x10
435#define BCSR2_USBPWREN 0x20
436#define BCSR2_USBSPD 0x40
437#define BCSR2_USBSUSP 0x80
438
439#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
440#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
441#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
442#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
443#define BCSR3_D27 0x10 /* Dip Switch settings */
444#define BCSR3_D26 0x20
445#define BCSR3_D25 0x40
446#define BCSR3_D24 0x80
447
448#endif /* __CONFIG_H */