blob: dc8fd03d808da491d141eb899fbbb96add664ee2 [file] [log] [blame]
Simon Glass00f37322015-04-14 21:03:40 -06001/*
2 * Copyright (c) 2011-2013, NVIDIA Corporation.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#ifndef _VIDEO_TEGRA124_SOR_H
8#define _VIDEO_TEGRA124_SOR_H
9
10#define SUPER_STATE0 0x1
11#define SUPER_STATE0_UPDATE_SHIFT 0
12#define SUPER_STATE0_UPDATE_DEFAULT_MASK 0x1
13#define SUPER_STATE1 0x2
14#define SUPER_STATE1_ATTACHED_SHIFT 3
15#define SUPER_STATE1_ATTACHED_NO (0 << 3)
16#define SUPER_STATE1_ATTACHED_YES (1 << 3)
17#define SUPER_STATE1_ASY_ORMODE_SHIFT 2
18#define SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2)
19#define SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2)
20#define SUPER_STATE1_ASY_HEAD_OP_SHIFT 0
21#define SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK 0x3
22#define SUPER_STATE1_ASY_HEAD_OP_SLEEP 0
23#define SUPER_STATE1_ASY_HEAD_OP_SNOOZE 1
24#define SUPER_STATE1_ASY_HEAD_OP_AWAKE 2
25#define STATE0 0x3
26#define STATE0_UPDATE_SHIFT 0
27#define STATE0_UPDATE_DEFAULT_MASK 0x1
28#define STATE1 0x4
29#define STATE1_ASY_PIXELDEPTH_SHIFT 17
30#define STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17)
31#define STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17)
32#define STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17)
33#define STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17)
34#define STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17)
35#define STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17)
36#define STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17)
37#define STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17)
38#define STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17)
39#define STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17)
40#define STATE1_ASY_REPLICATE_SHIFT 15
41#define STATE1_ASY_REPLICATE_DEFAULT_MASK (3 << 15)
42#define STATE1_ASY_REPLICATE_OFF (0 << 15)
43#define STATE1_ASY_REPLICATE_X2 (1 << 15)
44#define STATE1_ASY_REPLICATE_X4 (2 << 15)
45#define STATE1_ASY_DEPOL_SHIFT 14
46#define STATE1_ASY_DEPOL_DEFAULT_MASK (1 << 14)
47#define STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14)
48#define STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14)
49#define STATE1_ASY_VSYNCPOL_SHIFT 13
50#define STATE1_ASY_VSYNCPOL_DEFAULT_MASK (1 << 13)
51#define STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13)
52#define STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13)
53#define STATE1_ASY_HSYNCPOL_SHIFT 12
54#define STATE1_ASY_HSYNCPOL_DEFAULT_MASK (1 << 12)
55#define STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12)
56#define STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12)
57#define STATE1_ASY_PROTOCOL_SHIFT 8
58#define STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8)
59#define STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8)
60#define STATE1_ASY_PROTOCOL_DP_A (8 << 8)
61#define STATE1_ASY_PROTOCOL_DP_B (9 << 8)
62#define STATE1_ASY_PROTOCOL_CUSTOM (15 << 8)
63#define STATE1_ASY_CRCMODE_SHIFT 6
64#define STATE1_ASY_CRCMODE_DEFAULT_MASK (3 << 6)
65#define STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6)
66#define STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6)
67#define STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6)
68#define STATE1_ASY_SUBOWNER_SHIFT 4
69#define STATE1_ASY_SUBOWNER_DEFAULT_MASK (3 << 4)
70#define STATE1_ASY_SUBOWNER_NONE (0 << 4)
71#define STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
72#define STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
73#define STATE1_ASY_SUBOWNER_BOTH (3 << 4)
74#define STATE1_ASY_OWNER_SHIFT 0
75#define STATE1_ASY_OWNER_DEFAULT_MASK 0xf
76#define STATE1_ASY_OWNER_NONE 0
77#define STATE1_ASY_OWNER_HEAD0 1
78#define STATE1_ASY_OWNER_HEAD1 2
79#define NV_HEAD_STATE0(i) 0x5
80#define NV_HEAD_STATE0_INTERLACED_SHIFT 4
81#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (3 << 4)
82#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4)
83#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4)
84#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT 3
85#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (1 << 3)
86#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3)
87#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3)
88#define NV_HEAD_STATE0_DYNRANGE_SHIFT 2
89#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (1 << 2)
90#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2)
91#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2)
92#define NV_HEAD_STATE0_COLORSPACE_SHIFT 0
93#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK 0x3
94#define NV_HEAD_STATE0_COLORSPACE_RGB 0
95#define NV_HEAD_STATE0_COLORSPACE_YUV_601 1
96#define NV_HEAD_STATE0_COLORSPACE_YUV_709 2
97#define NV_HEAD_STATE1(i) (7 + i)
98#define NV_HEAD_STATE1_VTOTAL_SHIFT 16
99#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
100#define NV_HEAD_STATE1_HTOTAL_SHIFT 0
101#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK 0x7fff
102#define NV_HEAD_STATE2(i) (9 + i)
103#define NV_HEAD_STATE2_VSYNC_END_SHIFT 16
104#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
105#define NV_HEAD_STATE2_HSYNC_END_SHIFT 0
106#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK 0x7fff
107#define NV_HEAD_STATE3(i) (0xb + i)
108#define NV_HEAD_STATE3_VBLANK_END_SHIFT 16
109#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
110#define NV_HEAD_STATE3_HBLANK_END_SHIFT 0
111#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK 0x7fff
112#define NV_HEAD_STATE4(i) (0xd + i)
113#define NV_HEAD_STATE4_VBLANK_START_SHIFT 16
114#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
115#define NV_HEAD_STATE4_HBLANK_START_SHIFT 0
116#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK 0x7fff
117#define NV_HEAD_STATE5(i) (0xf + i)
118#define CRC_CNTRL 0x11
119#define CRC_CNTRL_ARM_CRC_ENABLE_SHIFT 0
120#define CRC_CNTRL_ARM_CRC_ENABLE_NO 0
121#define CRC_CNTRL_ARM_CRC_ENABLE_YES 1
122#define CRC_CNTRL_ARM_CRC_ENABLE_DIS 0
123#define CRC_CNTRL_ARM_CRC_ENABLE_EN 1
124#define CLK_CNTRL 0x13
125#define CLK_CNTRL_DP_CLK_SEL_SHIFT 0
126#define CLK_CNTRL_DP_CLK_SEL_MASK 0x3
127#define CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK 0
128#define CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK 1
129#define CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK 2
130#define CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK 3
131#define CLK_CNTRL_DP_LINK_SPEED_SHIFT 2
132#define CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
133#define CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2)
134#define CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2)
135#define CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2)
136#define CAP 0x14
137#define CAP_DP_A_SHIFT 24
138#define CAP_DP_A_DEFAULT_MASK (1 << 24)
139#define CAP_DP_A_FALSE (0 << 24)
140#define CAP_DP_A_TRUE (1 << 24)
141#define CAP_DP_B_SHIFT 25
142#define CAP_DP_B_DEFAULT_MASK (1 << 24)
143#define CAP_DP_B_FALSE (0 << 24)
144#define CAP_DP_B_TRUE (1 << 24)
145#define PWR 0x15
146#define PWR_SETTING_NEW_SHIFT 31
147#define PWR_SETTING_NEW_DEFAULT_MASK (1 << 31)
148#define PWR_SETTING_NEW_DONE (0 << 31)
149#define PWR_SETTING_NEW_PENDING (1 << 31)
150#define PWR_SETTING_NEW_TRIGGER (1 << 31)
151#define PWR_MODE_SHIFT 28
152#define PWR_MODE_DEFAULT_MASK (1 << 28)
153#define PWR_MODE_NORMAL (0 << 28)
154#define PWR_MODE_SAFE (1 << 28)
155#define PWR_HALT_DELAY_SHIFT 24
156#define PWR_HALT_DELAY_DEFAULT_MASK (1 << 24)
157#define PWR_HALT_DELAY_DONE (0 << 24)
158#define PWR_HALT_DELAY_ACTIVE (1 << 24)
159#define PWR_SAFE_START_SHIFT 17
160#define PWR_SAFE_START_DEFAULT_MASK (1 << 17)
161#define PWR_SAFE_START_NORMAL (0 << 17)
162#define PWR_SAFE_START_ALT (1 << 17)
163#define PWR_SAFE_STATE_SHIFT 16
164#define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16)
165#define PWR_SAFE_STATE_PD (0 << 16)
166#define PWR_SAFE_STATE_PU (1 << 16)
167#define PWR_NORMAL_START_SHIFT 1
168#define PWR_NORMAL_START_DEFAULT_MASK (1 << 1)
169#define PWR_NORMAL_START_NORMAL (0 << 16)
170#define PWR_NORMAL_START_ALT (1 << 16)
171#define PWR_NORMAL_STATE_SHIFT 0
172#define PWR_NORMAL_STATE_DEFAULT_MASK 0x1
173#define PWR_NORMAL_STATE_PD 0
174#define PWR_NORMAL_STATE_PU 1
175#define TEST 0x16
176#define TEST_TESTMUX_SHIFT 24
177#define TEST_TESTMUX_DEFAULT_MASK (0xff << 24)
178#define TEST_TESTMUX_AVSS (0 << 24)
179#define TEST_TESTMUX_CLOCKIN (2 << 24)
180#define TEST_TESTMUX_PLL_VOL (4 << 24)
181#define TEST_TESTMUX_SLOWCLKINT (8 << 24)
182#define TEST_TESTMUX_AVDD (16 << 24)
183#define TEST_TESTMUX_VDDREG (32 << 24)
184#define TEST_TESTMUX_REGREF_VDDREG (64 << 24)
185#define TEST_TESTMUX_REGREF_AVDD (128 << 24)
186#define TEST_CRC_SHIFT 23
187#define TEST_CRC_PRE_SERIALIZE (0 << 23)
188#define TEST_CRC_POST_DESERIALIZE (1 << 23)
189#define TEST_TPAT_SHIFT 20
190#define TEST_TPAT_DEFAULT_MASK (7 << 20)
191#define TEST_TPAT_LO (0 << 20)
192#define TEST_TPAT_TDAT (1 << 20)
193#define TEST_TPAT_RAMP (2 << 20)
194#define TEST_TPAT_WALK (3 << 20)
195#define TEST_TPAT_MAXSTEP (4 << 20)
196#define TEST_TPAT_MINSTEP (5 << 20)
197#define TEST_DSRC_SHIFT 16
198#define TEST_DSRC_DEFAULT_MASK (3 << 16)
199#define TEST_DSRC_NORMAL (0 << 16)
200#define TEST_DSRC_DEBUG (1 << 16)
201#define TEST_DSRC_TGEN (2 << 16)
202#define TEST_HEAD_NUMBER_SHIFT 12
203#define TEST_HEAD_NUMBER_DEFAULT_MASK (3 << 12)
204#define TEST_HEAD_NUMBER_NONE (0 << 12)
205#define TEST_HEAD_NUMBER_HEAD0 (1 << 12)
206#define TEST_HEAD_NUMBER_HEAD1 (2 << 12)
207#define TEST_ATTACHED_SHIFT 10
208#define TEST_ATTACHED_DEFAULT_MASK (1 << 10)
209#define TEST_ATTACHED_FALSE (0 << 10)
210#define TEST_ATTACHED_TRUE (1 << 10)
211#define TEST_ACT_HEAD_OPMODE_SHIFT 8
212#define TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (3 << 8)
213#define TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8)
214#define TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8)
215#define TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8)
216#define TEST_INVD_SHIFT 6
217#define TEST_INVD_DISABLE (0 << 6)
218#define TEST_INVD_ENABLE (1 << 6)
219#define TEST_TEST_ENABLE_SHIFT 1
220#define TEST_TEST_ENABLE_DISABLE (0 << 1)
221#define TEST_TEST_ENABLE_ENABLE (1 << 1)
222#define PLL0 0x17
223#define PLL0_ICHPMP_SHFIT 24
224#define PLL0_ICHPMP_DEFAULT_MASK (0xf << 24)
225#define PLL0_VCOCAP_SHIFT 8
226#define PLL0_VCOCAP_DEFAULT_MASK (0xf << 8)
227#define PLL0_PLLREG_LEVEL_SHIFT 6
228#define PLL0_PLLREG_LEVEL_DEFAULT_MASK (3 << 6)
229#define PLL0_PLLREG_LEVEL_V25 (0 << 6)
230#define PLL0_PLLREG_LEVEL_V15 (1 << 6)
231#define PLL0_PLLREG_LEVEL_V35 (2 << 6)
232#define PLL0_PLLREG_LEVEL_V45 (3 << 6)
233#define PLL0_PULLDOWN_SHIFT 5
234#define PLL0_PULLDOWN_DEFAULT_MASK (1 << 5)
235#define PLL0_PULLDOWN_DISABLE (0 << 5)
236#define PLL0_PULLDOWN_ENABLE (1 << 5)
237#define PLL0_RESISTORSEL_SHIFT 4
238#define PLL0_RESISTORSEL_DEFAULT_MASK (1 << 4)
239#define PLL0_RESISTORSEL_INT (0 << 4)
240#define PLL0_RESISTORSEL_EXT (1 << 4)
241#define PLL0_VCOPD_SHIFT 2
242#define PLL0_VCOPD_MASK (1 << 2)
243#define PLL0_VCOPD_RESCIND (0 << 2)
244#define PLL0_VCOPD_ASSERT (1 << 2)
245#define PLL0_PWR_SHIFT 0
246#define PLL0_PWR_MASK 1
247#define PLL0_PWR_ON 0
248#define PLL0_PWR_OFF 1
249#define PLL1_TMDS_TERM_SHIFT 8
250#define PLL1_TMDS_TERM_DISABLE (0 << 8)
251#define PLL1_TMDS_TERM_ENABLE (1 << 8)
252#define PLL1 0x18
253#define PLL1_TERM_COMPOUT_SHIFT 15
254#define PLL1_TERM_COMPOUT_LOW (0 << 15)
255#define PLL1_TERM_COMPOUT_HIGH (1 << 15)
256#define PLL2 0x19
257#define PLL2_DCIR_PLL_RESET_SHIFT 0
258#define PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0)
259#define PLL2_DCIR_PLL_RESET_ALLOW (1 << 0)
260#define PLL2_AUX1_SHIFT 17
261#define PLL2_AUX1_SEQ_MASK (1 << 17)
262#define PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17)
263#define PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17)
264#define PLL2_AUX2_SHIFT 18
265#define PLL2_AUX2_MASK (1 << 18)
266#define PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18)
267#define PLL2_AUX2_ALLOW_POWERDOWN (1 << 18)
268#define PLL2_AUX6_SHIFT 22
269#define PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22)
270#define PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22)
271#define PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22)
272#define PLL2_AUX7_SHIFT 23
273#define PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23)
274#define PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23)
275#define PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23)
276#define PLL2_AUX8_SHIFT 24
277#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24)
278#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24)
279#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24)
280#define PLL2_AUX9_SHIFT 25
281#define PLL2_AUX9_LVDSEN_ALLOW (0 << 25)
282#define PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25)
283#define PLL3 0x1a
284#define PLL3_PLLVDD_MODE_SHIFT 13
285#define PLL3_PLLVDD_MODE_MASK (1 << 13)
286#define PLL3_PLLVDD_MODE_V1_8 (0 << 13)
287#define PLL3_PLLVDD_MODE_V3_3 (1 << 13)
288#define CSTM 0x1b
289#define CSTM_ROTDAT_SHIFT 28
290#define CSTM_ROTDAT_DEFAULT_MASK (7 << 28)
291#define CSTM_ROTCLK_SHIFT 24
292#define CSTM_ROTCLK_DEFAULT_MASK (0xf << 24)
293#define CSTM_LVDS_EN_SHIFT 16
294#define CSTM_LVDS_EN_DISABLE (0 << 16)
295#define CSTM_LVDS_EN_ENABLE (1 << 16)
296#define CSTM_LINKACTB_SHIFT 15
297#define CSTM_LINKACTB_DISABLE (0 << 15)
298#define CSTM_LINKACTB_ENABLE (1 << 15)
299#define CSTM_LINKACTA_SHIFT 14
300#define CSTM_LINKACTA_DISABLE (0 << 14)
301#define CSTM_LINKACTA_ENABLE (1 << 14)
302#define LVDS 0x1c
303#define LVDS_ROTDAT_SHIFT 28
304#define LVDS_ROTDAT_DEFAULT_MASK (7 << 28)
305#define LVDS_ROTDAT_RST (0 << 28)
306#define LVDS_ROTCLK_SHIFT 24
307#define LVDS_ROTCLK_DEFAULT_MASK (0xf << 24)
308#define LVDS_ROTCLK_RST (0 << 24)
309#define LVDS_PLLDIV_SHIFT 21
310#define LVDS_PLLDIV_DEFAULT_MASK (1 << 21)
311#define LVDS_PLLDIV_BY_7 (0 << 21)
312#define LVDS_BALANCED_SHIFT 19
313#define LVDS_BALANCED_DEFAULT_MASK (1 << 19)
314#define LVDS_BALANCED_DISABLE (0 << 19)
315#define LVDS_BALANCED_ENABLE (1 << 19)
316#define LVDS_NEW_MODE_SHIFT 18
317#define LVDS_NEW_MODE_DEFAULT_MASK (1 << 18)
318#define LVDS_NEW_MODE_DISABLE (0 << 18)
319#define LVDS_NEW_MODE_ENABLE (1 << 18)
320#define LVDS_DUP_SYNC_SHIFT 17
321#define LVDS_DUP_SYNC_DEFAULT_MASK (1 << 17)
322#define LVDS_DUP_SYNC_DISABLE (0 << 17)
323#define LVDS_DUP_SYNC_ENABLE (1 << 17)
324#define LVDS_LVDS_EN_SHIFT 16
325#define LVDS_LVDS_EN_DEFAULT_MASK (1 << 16)
326#define LVDS_LVDS_EN_ENABLE (1 << 16)
327#define LVDS_LINKACTB_SHIFT 15
328#define LVDS_LINKACTB_DEFAULT_MASK (1 << 15)
329#define LVDS_LINKACTB_DISABLE (0 << 15)
330#define LVDS_LINKACTB_ENABLE (1 << 15)
331#define LVDS_LINKACTA_SHIFT 14
332#define LVDS_LINKACTA_DEFAULT_MASK (1 << 14)
333#define LVDS_LINKACTA_ENABLE (1 << 14)
334#define LVDS_MODE_SHIFT 12
335#define LVDS_MODE_DEFAULT_MASK (3 << 12)
336#define LVDS_MODE_LVDS (0 << 12)
337#define LVDS_UPPER_SHIFT 11
338#define LVDS_UPPER_DEFAULT_MASK (1 << 11)
339#define LVDS_UPPER_FALSE (0 << 11)
340#define LVDS_UPPER_TRUE (1 << 11)
341#define LVDS_PD_TXCB_SHIFT 9
342#define LVDS_PD_TXCB_DEFAULT_MASK (1 << 9)
343#define LVDS_PD_TXCB_ENABLE (0 << 9)
344#define LVDS_PD_TXCB_DISABLE (1 << 9)
345#define LVDS_PD_TXCA_SHIFT 8
346#define LVDS_PD_TXCA_DEFAULT_MASK (1 << 8)
347#define LVDS_PD_TXCA_ENABLE (0 << 8)
348#define LVDS_PD_TXDB_3_SHIFT 7
349#define LVDS_PD_TXDB_3_DEFAULT_MASK (1 << 7)
350#define LVDS_PD_TXDB_3_ENABLE (0 << 7)
351#define LVDS_PD_TXDB_3_DISABLE (1 << 7)
352#define LVDS_PD_TXDB_2_SHIFT 6
353#define LVDS_PD_TXDB_2_DEFAULT_MASK (1 << 6)
354#define LVDS_PD_TXDB_2_ENABLE (0 << 6)
355#define LVDS_PD_TXDB_2_DISABLE (1 << 6)
356#define LVDS_PD_TXDB_1_SHIFT 5
357#define LVDS_PD_TXDB_1_DEFAULT_MASK (1 << 5)
358#define LVDS_PD_TXDB_1_ENABLE (0 << 5)
359#define LVDS_PD_TXDB_1_DISABLE (1 << 5)
360#define LVDS_PD_TXDB_0_SHIFT 4
361#define LVDS_PD_TXDB_0_DEFAULT_MASK (1 << 4)
362#define LVDS_PD_TXDB_0_ENABLE (0 << 4)
363#define LVDS_PD_TXDB_0_DISABLE (1 << 4)
364#define LVDS_PD_TXDA_3_SHIFT 3
365#define LVDS_PD_TXDA_3_DEFAULT_MASK (1 << 3)
366#define LVDS_PD_TXDA_3_ENABLE (0 << 3)
367#define LVDS_PD_TXDA_3_DISABLE (1 << 3)
368#define LVDS_PD_TXDA_2_SHIFT 2
369#define LVDS_PD_TXDA_2_DEFAULT_MASK (1 << 2)
370#define LVDS_PD_TXDA_2_ENABLE (0 << 2)
371#define LVDS_PD_TXDA_1_SHIFT 1
372#define LVDS_PD_TXDA_1_DEFAULT_MASK (1 << 1)
373#define LVDS_PD_TXDA_1_ENABLE (0 << 1)
374#define LVDS_PD_TXDA_0_SHIFT 0
375#define LVDS_PD_TXDA_0_DEFAULT_MASK 0x1
376#define LVDS_PD_TXDA_0_ENABLE 0
377#define CRCA 0x1d
378#define CRCA_VALID_FALSE 0
379#define CRCA_VALID_TRUE 1
380#define CRCA_VALID_RST 1
381#define CRCB 0x1e
382#define CRCB_CRC_DEFAULT_MASK 0xffffffff
383#define SEQ_CTL 0x20
384#define SEQ_CTL_SWITCH_SHIFT 30
385#define SEQ_CTL_SWITCH_MASK (1 << 30)
386#define SEQ_CTL_SWITCH_WAIT (0 << 30)
387#define SEQ_CTL_SWITCH_FORCE (1 << 30)
388#define SEQ_CTL_STATUS_SHIFT 28
389#define SEQ_CTL_STATUS_MASK (1 << 28)
390#define SEQ_CTL_STATUS_STOPPED (0 << 28)
391#define SEQ_CTL_STATUS_RUNNING (1 << 28)
392#define SEQ_CTL_PC_SHIFT 16
393#define SEQ_CTL_PC_MASK (0xf << 16)
394#define SEQ_CTL_PD_PC_ALT_SHIFT 12
395#define SEQ_CTL_PD_PC_ALT_MASK (0xf << 12)
396#define SEQ_CTL_PD_PC_SHIFT 8
397#define SEQ_CTL_PD_PC_MASK (0xf << 8)
398#define SEQ_CTL_PU_PC_ALT_SHIFT 4
399#define SEQ_CTL_PU_PC_ALT_MASK (0xf << 4)
400#define SEQ_CTL_PU_PC_SHIFT 0
401#define SEQ_CTL_PU_PC_MASK 0xf
402#define LANE_SEQ_CTL 0x21
403#define LANE_SEQ_CTL_SETTING_NEW_SHIFT 31
404#define LANE_SEQ_CTL_SETTING_MASK (1 << 31)
405#define LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31)
406#define LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31)
407#define LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31)
408#define LANE_SEQ_CTL_SEQ_STATE_SHIFT 28
409#define LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28)
410#define LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28)
411#define LANE_SEQ_CTL_SEQUENCE_SHIFT 20
412#define LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
413#define LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
414#define LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT 16
415#define LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16)
416#define LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16)
417#define LANE_SEQ_CTL_DELAY_SHIFT 12
418#define LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12)
419#define LANE_SEQ_CTL_LANE9_STATE_SHIFT 9
420#define LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9)
421#define LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9)
422#define LANE_SEQ_CTL_LANE8_STATE_SHIFT 8
423#define LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8)
424#define LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8)
425#define LANE_SEQ_CTL_LANE7_STATE_SHIFT 7
426#define LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7)
427#define LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7)
428#define LANE_SEQ_CTL_LANE6_STATE_SHIFT 6
429#define LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6)
430#define LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6)
431#define LANE_SEQ_CTL_LANE5_STATE_SHIFT 5
432#define LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5)
433#define LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5)
434#define LANE_SEQ_CTL_LANE4_STATE_SHIFT 4
435#define LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4)
436#define LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4)
437#define LANE_SEQ_CTL_LANE3_STATE_SHIFT 3
438#define LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3)
439#define LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3)
440#define LANE_SEQ_CTL_LANE2_STATE_SHIFT 2
441#define LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2)
442#define LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2)
443#define LANE_SEQ_CTL_LANE1_STATE_SHIFT 1
444#define LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1)
445#define LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1)
446#define LANE_SEQ_CTL_LANE0_STATE_SHIFT 0
447#define LANE_SEQ_CTL_LANE0_STATE_POWERUP 0
448#define LANE_SEQ_CTL_LANE0_STATE_POWERDOWN 1
449#define SEQ_INST(i) (0x22 + i)
450#define SEQ_INST_PLL_PULLDOWN_SHIFT 31
451#define SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31)
452#define SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31)
453#define SEQ_INST_POWERDOWN_MACRO_SHIFT 30
454#define SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30)
455#define SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30)
456#define SEQ_INST_ASSERT_PLL_RESET_SHIFT 29
457#define SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29)
458#define SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29)
459#define SEQ_INST_BLANK_V_SHIFT 28
460#define SEQ_INST_BLANK_V_NORMAL (0 << 28)
461#define SEQ_INST_BLANK_V_INACTIVE (1 << 28)
462#define SEQ_INST_BLANK_H_SHIFT 27
463#define SEQ_INST_BLANK_H_NORMAL (0 << 27)
464#define SEQ_INST_BLANK_H_INACTIVE (1 << 27)
465#define SEQ_INST_BLANK_DE_SHIFT 26
466#define SEQ_INST_BLANK_DE_NORMAL (0 << 26)
467#define SEQ_INST_BLANK_DE_INACTIVE (1 << 26)
468#define SEQ_INST_BLACK_DATA_SHIFT 25
469#define SEQ_INST_BLACK_DATA_NORMAL (0 << 25)
470#define SEQ_INST_BLACK_DATA_BLACK (1 << 25)
471#define SEQ_INST_TRISTATE_IOS_SHIFT 24
472#define SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24)
473#define SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24)
474#define SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT 23
475#define SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23)
476#define SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23)
477#define SEQ_INST_PIN_B_SHIFT 22
478#define SEQ_INST_PIN_B_LOW (0 << 22)
479#define SEQ_INST_PIN_B_HIGH (1 << 22)
480#define SEQ_INST_PIN_A_SHIFT 21
481#define SEQ_INST_PIN_A_LOW (0 << 21)
482#define SEQ_INST_PIN_A_HIGH (1 << 21)
483#define SEQ_INST_SEQUENCE_SHIFT 19
484#define SEQ_INST_SEQUENCE_UP (0 << 19)
485#define SEQ_INST_SEQUENCE_DOWN (1 << 19)
486#define SEQ_INST_LANE_SEQ_SHIFT 18
487#define SEQ_INST_LANE_SEQ_STOP (0 << 18)
488#define SEQ_INST_LANE_SEQ_RUN (1 << 18)
489#define SEQ_INST_PDPORT_SHIFT 17
490#define SEQ_INST_PDPORT_NO (0 << 17)
491#define SEQ_INST_PDPORT_YES (1 << 17)
492#define SEQ_INST_PDPLL_SHIFT 16
493#define SEQ_INST_PDPLL_NO (0 << 16)
494#define SEQ_INST_PDPLL_YES (1 << 16)
495#define SEQ_INST_HALT_SHIFT 15
496#define SEQ_INST_HALT_FALSE (0 << 15)
497#define SEQ_INST_HALT_TRUE (1 << 15)
498#define SEQ_INST_WAIT_UNITS_SHIFT 12
499#define SEQ_INST_WAIT_UNITS_DEFAULT_MASK (3 << 12)
500#define SEQ_INST_WAIT_UNITS_US (0 << 12)
501#define SEQ_INST_WAIT_UNITS_MS (1 << 12)
502#define SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
503#define SEQ_INST_WAIT_TIME_SHIFT 0
504#define SEQ_INST_WAIT_TIME_DEFAULT_MASK 0x3ff
505#define PWM_DIV 0x32
506#define PWM_DIV_DIVIDE_DEFAULT_MASK 0xffffff
507#define PWM_CTL 0x33
508#define PWM_CTL_SETTING_NEW_SHIFT 31
509#define PWM_CTL_SETTING_NEW_DONE (0 << 31)
510#define PWM_CTL_SETTING_NEW_PENDING (1 << 31)
511#define PWM_CTL_SETTING_NEW_TRIGGER (1 << 31)
512#define PWM_CTL_CLKSEL_SHIFT 30
513#define PWM_CTL_CLKSEL_PCLK (0 << 30)
514#define PWM_CTL_CLKSEL_XTAL (1 << 30)
515#define PWM_CTL_DUTY_CYCLE_SHIFT 0
516#define PWM_CTL_DUTY_CYCLE_MASK 0xffffff
517#define MSCHECK 0x49
518#define MSCHECK_CTL_SHIFT 31
519#define MSCHECK_CTL_CLEAR (0 << 31)
520#define MSCHECK_CTL_RUN (1 << 31)
521#define XBAR_CTRL 0x4a
522#define DP_LINKCTL(i) (0x4c + (i))
523#define DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT 31
524#define DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31)
525#define DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31)
526#define DP_LINKCTL_COMPLIANCEPTTRN_SHIFT 28
527#define DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28)
528#define DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28)
529#define DP_LINKCTL_LANECOUNT_SHIFT 16
530#define DP_LINKCTL_LANECOUNT_MASK (0x1f << 16)
531#define DP_LINKCTL_LANECOUNT_ZERO (0 << 16)
532#define DP_LINKCTL_LANECOUNT_ONE (1 << 16)
533#define DP_LINKCTL_LANECOUNT_TWO (3 << 16)
534#define DP_LINKCTL_LANECOUNT_FOUR (15 << 16)
535#define DP_LINKCTL_ENHANCEDFRAME_SHIFT 14
536#define DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14)
537#define DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14)
538#define DP_LINKCTL_SYNCMODE_SHIFT 10
539#define DP_LINKCTL_SYNCMODE_DISABLE (0 << 10)
540#define DP_LINKCTL_SYNCMODE_ENABLE (1 << 10)
541#define DP_LINKCTL_TUSIZE_SHIFT 2
542#define DP_LINKCTL_TUSIZE_MASK (0x7f << 2)
543#define DP_LINKCTL_ENABLE_SHIFT 0
544#define DP_LINKCTL_ENABLE_NO 0
545#define DP_LINKCTL_ENABLE_YES 1
546#define DC(i) (0x4e + (i))
547#define DC_LANE3_DP_LANE3_SHIFT 24
548#define DC_LANE3_DP_LANE3_MASK (0xff << 24)
549#define DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24)
550#define DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24)
551#define DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24)
552#define DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24)
553#define DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24)
554#define DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24)
555#define DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24)
556#define DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24)
557#define DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24)
558#define DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24)
559#define DC_LANE2_DP_LANE0_SHIFT 16
560#define DC_LANE2_DP_LANE0_MASK (0xff << 16)
561#define DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16)
562#define DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16)
563#define DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16)
564#define DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16)
565#define DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16)
566#define DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16)
567#define DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16)
568#define DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16)
569#define DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16)
570#define DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16)
571#define DC_LANE1_DP_LANE1_SHIFT 8
572#define DC_LANE1_DP_LANE1_MASK (0xff << 8)
573#define DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8)
574#define DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8)
575#define DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8)
576#define DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8)
577#define DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8)
578#define DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8)
579#define DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8)
580#define DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8)
581#define DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8)
582#define DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8)
583#define DC_LANE0_DP_LANE2_SHIFT 0
584#define DC_LANE0_DP_LANE2_MASK 0xff
585#define DC_LANE0_DP_LANE2_P0_LEVEL0 17
586#define DC_LANE0_DP_LANE2_P1_LEVEL0 21
587#define DC_LANE0_DP_LANE2_P2_LEVEL0 26
588#define DC_LANE0_DP_LANE2_P3_LEVEL0 34
589#define DC_LANE0_DP_LANE2_P0_LEVEL1 26
590#define DC_LANE0_DP_LANE2_P1_LEVEL1 32
591#define DC_LANE0_DP_LANE2_P2_LEVEL1 39
592#define DC_LANE0_DP_LANE2_P0_LEVEL2 34
593#define DC_LANE0_DP_LANE2_P1_LEVEL2 43
594#define DC_LANE0_DP_LANE2_P0_LEVEL3 51
595#define LANE_DRIVE_CURRENT(i) (0x4e + (i))
596#define PR(i) (0x52 + (i))
597#define PR_LANE3_DP_LANE3_SHIFT 24
598#define PR_LANE3_DP_LANE3_MASK (0xff << 24)
599#define PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24)
600#define PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24)
601#define PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24)
602#define PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24)
603#define PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24)
604#define PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24)
605#define PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24)
606#define PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24)
607#define PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24)
608#define PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24)
609#define PR_LANE2_DP_LANE0_SHIFT 16
610#define PR_LANE2_DP_LANE0_MASK (0xff << 16)
611#define PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16)
612#define PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16)
613#define PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16)
614#define PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16)
615#define PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16)
616#define PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16)
617#define PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16)
618#define PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16)
619#define PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16)
620#define PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16)
621#define PR_LANE1_DP_LANE1_SHIFT 8
622#define PR_LANE1_DP_LANE1_MASK (0xff >> 8)
623#define PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8)
624#define PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8)
625#define PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8)
626#define PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8)
627#define PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8)
628#define PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8)
629#define PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8)
630#define PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8)
631#define PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8)
632#define PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8)
633#define PR_LANE0_DP_LANE2_SHIFT 0
634#define PR_LANE0_DP_LANE2_MASK 0xff
635#define PR_LANE0_DP_LANE2_D0_LEVEL0 0
636#define PR_LANE0_DP_LANE2_D1_LEVEL0 0
637#define PR_LANE0_DP_LANE2_D2_LEVEL0 0
638#define PR_LANE0_DP_LANE2_D3_LEVEL0 0
639#define PR_LANE0_DP_LANE2_D0_LEVEL1 4
640#define PR_LANE0_DP_LANE2_D1_LEVEL1 6
641#define PR_LANE0_DP_LANE2_D2_LEVEL1 17
642#define PR_LANE0_DP_LANE2_D0_LEVEL2 8
643#define PR_LANE0_DP_LANE2_D1_LEVEL2 13
644#define PR_LANE0_DP_LANE2_D0_LEVEL3 17
645#define LANE4_PREEMPHASIS(i) (0x54 + (i))
646#define POSTCURSOR(i) (0x56 + (i))
647#define DP_CONFIG(i) (0x58 + (i))
648#define DP_CONFIG_RD_RESET_VAL_SHIFT 31
649#define DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31)
650#define DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31)
651#define DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT 28
652#define DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28)
653#define DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28)
654#define DP_CONFIG_ACTIVESYM_CNTL_SHIFT 26
655#define DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26)
656#define DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26)
657#define DP_CONFIG_ACTIVESYM_POLARITY_SHIFT 24
658#define DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24)
659#define DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24)
660#define DP_CONFIG_ACTIVESYM_FRAC_SHIFT 16
661#define DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16)
662#define DP_CONFIG_ACTIVESYM_COUNT_SHIFT 8
663#define DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8)
664#define DP_CONFIG_WATERMARK_SHIFT 0
665#define DP_CONFIG_WATERMARK_MASK 0x3f
666#define DP_MN(i) (0x5a + i)
667#define DP_MN_M_MOD_SHIFT 30
668#define DP_MN_M_MOD_DEFAULT_MASK (3 << 30)
669#define DP_MN_M_MOD_NONE (0 << 30)
670#define DP_MN_M_MOD_INC (1 << 30)
671#define DP_MN_M_MOD_DEC (2 << 30)
672#define DP_MN_M_DELTA_SHIFT 24
673#define DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24)
674#define DP_MN_N_VAL_SHIFT 0
675#define DP_MN_N_VAL_DEFAULT_MASK 0xffffff
676#define DP_PADCTL(i) (0x5c + (i))
677#define DP_PADCTL_SPARE_SHIFT 25
678#define DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25)
679#define DP_PADCTL_VCO_2X_SHIFT 24
680#define DP_PADCTL_VCO_2X_DISABLE (0 << 24)
681#define DP_PADCTL_VCO_2X_ENABLE (1 << 24)
682#define DP_PADCTL_PAD_CAL_PD_SHIFT 23
683#define DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23)
684#define DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23)
685#define DP_PADCTL_TX_PU_SHIFT 22
686#define DP_PADCTL_TX_PU_DISABLE (0 << 22)
687#define DP_PADCTL_TX_PU_ENABLE (1 << 22)
688#define DP_PADCTL_TX_PU_MASK (1 << 22)
689#define DP_PADCTL_REG_CTRL_SHIFT 20
690#define DP_PADCTL_REG_CTRL_DEFAULT_MASK (3 << 20)
691#define DP_PADCTL_VCMMODE_SHIFT 16
692#define DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16)
693#define DP_PADCTL_VCMMODE_TRISTATE (0 << 16)
694#define DP_PADCTL_VCMMODE_TEST_MUX (1 << 16)
695#define DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16)
696#define DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16)
697#define DP_PADCTL_TX_PU_VALUE_SHIFT 8
698#define DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8)
699#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT 7
700#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
701#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7)
702#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT 6
703#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
704#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6)
705#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT 5
706#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
707#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5)
708#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT 4
709#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
710#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4)
711#define DP_PADCTL_PD_TXD_3_SHIFT 3
712#define DP_PADCTL_PD_TXD_3_YES (0 << 3)
713#define DP_PADCTL_PD_TXD_3_NO (1 << 3)
714#define DP_PADCTL_PD_TXD_0_SHIFT 2
715#define DP_PADCTL_PD_TXD_0_YES (0 << 2)
716#define DP_PADCTL_PD_TXD_0_NO (1 << 2)
717#define DP_PADCTL_PD_TXD_1_SHIFT 1
718#define DP_PADCTL_PD_TXD_1_YES (0 << 1)
719#define DP_PADCTL_PD_TXD_1_NO (1 << 1)
720#define DP_PADCTL_PD_TXD_2_SHIFT 0
721#define DP_PADCTL_PD_TXD_2_YES 0
722#define DP_PADCTL_PD_TXD_2_NO 1
723#define DP_DEBUG(i) (0x5e + i)
724#define DP_SPARE(i) (0x60 + (i))
725#define DP_SPARE_REG_SHIFT 3
726#define DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3)
727#define DP_SPARE_SOR_CLK_SEL_SHIFT 2
728#define DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (1 << 2)
729#define DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2)
730#define DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2)
731#define DP_SPARE_PANEL_SHIFT 1
732#define DP_SPARE_PANEL_EXTERNAL (0 << 1)
733#define DP_SPARE_PANEL_INTERNAL (1 << 1)
734#define DP_SPARE_SEQ_ENABLE_SHIFT 0
735#define DP_SPARE_SEQ_ENABLE_NO 0
736#define DP_SPARE_SEQ_ENABLE_YES 1
737#define DP_AUDIO_CTRL 0x62
738#define DP_AUDIO_HBLANK_SYMBOLS 0x63
739#define DP_AUDIO_HBLANK_SYMBOLS_MASK 0x1ffff
740#define DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT 0
741#define DP_AUDIO_VBLANK_SYMBOLS 0x64
742#define DP_AUDIO_VBLANK_SYMBOLS_MASK 0x1ffff
743#define DP_AUDIO_VBLANK_SYMBOLS_SHIFT 0
744#define DP_GENERIC_INFOFRAME_HEADER 0x65
745#define DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i))
746#define DP_TPG 0x6d
747#define DP_TPG_LANE3_CHANNELCODING_SHIFT 30
748#define DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30)
749#define DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30)
750#define DP_TPG_LANE3_SCRAMBLEREN_SHIFT 28
751#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28)
752#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28)
753#define DP_TPG_LANE3_PATTERN_SHIFT 24
754#define DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24)
755#define DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24)
756#define DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24)
757#define DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24)
758#define DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24)
759#define DP_TPG_LANE3_PATTERN_D102 (4 << 24)
760#define DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24)
761#define DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24)
762#define DP_TPG_LANE3_PATTERN_CSTM (7 << 24)
763#define DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24)
764#define DP_TPG_LANE2_CHANNELCODING_SHIFT 22
765#define DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22)
766#define DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22)
767#define DP_TPG_LANE2_SCRAMBLEREN_SHIFT 20
768#define DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (3 << 20)
769#define DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20)
770#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20)
771#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20)
772#define DP_TPG_LANE2_PATTERN_SHIFT 16
773#define DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16)
774#define DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16)
775#define DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16)
776#define DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16)
777#define DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16)
778#define DP_TPG_LANE2_PATTERN_D102 (4 << 16)
779#define DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16)
780#define DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16)
781#define DP_TPG_LANE2_PATTERN_CSTM (7 << 16)
782#define DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16)
783#define DP_TPG_LANE1_CHANNELCODING_SHIFT 14
784#define DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14)
785#define DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14)
786#define DP_TPG_LANE1_SCRAMBLEREN_SHIFT 12
787#define DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (3 << 12)
788#define DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12)
789#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12)
790#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
791#define DP_TPG_LANE1_PATTERN_SHIFT 8
792#define DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8)
793#define DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8)
794#define DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8)
795#define DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8)
796#define DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8)
797#define DP_TPG_LANE1_PATTERN_D102 (4 << 8)
798#define DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8)
799#define DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8)
800#define DP_TPG_LANE1_PATTERN_CSTM (7 << 8)
801#define DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8)
802#define DP_TPG_LANE0_CHANNELCODING_SHIFT 6
803#define DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6)
804#define DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6)
805#define DP_TPG_LANE0_SCRAMBLEREN_SHIFT 4
806#define DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (3 << 4)
807#define DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4)
808#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4)
809#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4)
810#define DP_TPG_LANE0_PATTERN_SHIFT 0
811#define DP_TPG_LANE0_PATTERN_DEFAULT_MASK 0xf
812#define DP_TPG_LANE0_PATTERN_NOPATTERN 0
813#define DP_TPG_LANE0_PATTERN_TRAINING1 1
814#define DP_TPG_LANE0_PATTERN_TRAINING2 2
815#define DP_TPG_LANE0_PATTERN_TRAINING3 3
816#define DP_TPG_LANE0_PATTERN_D102 4
817#define DP_TPG_LANE0_PATTERN_SBLERRRATE 5
818#define DP_TPG_LANE0_PATTERN_PRBS7 6
819#define DP_TPG_LANE0_PATTERN_CSTM 7
820#define DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 8
821
822enum {
823 training_pattern_disabled = 0,
824 training_pattern_1 = 1,
825 training_pattern_2 = 2,
826 training_pattern_3 = 3,
827 training_pattern_none = 0xff
828};
829
830enum tegra_dc_sor_protocol {
831 SOR_DP,
832 SOR_LVDS,
833};
834
835#define SOR_LINK_SPEED_G1_62 6
836#define SOR_LINK_SPEED_G2_7 10
837#define SOR_LINK_SPEED_G5_4 20
838#define SOR_LINK_SPEED_LVDS 7
839
840struct tegra_dp_link_config {
841 int is_valid;
842
843 /* Supported configuration */
844 u8 max_link_bw;
845 u8 max_lane_count;
846 int downspread;
847 int support_enhanced_framing;
848 u32 bits_per_pixel;
849 int alt_scramber_reset_cap; /* true for eDP */
850 int only_enhanced_framing; /* enhanced_frame_en ignored */
Simon Glassdedc44b2015-04-14 21:03:44 -0600851 int frame_in_ms;
Simon Glass00f37322015-04-14 21:03:40 -0600852
853 /* Actual configuration */
854 u8 link_bw;
855 u8 lane_count;
856 int enhanced_framing;
857 int scramble_ena;
858
859 u32 activepolarity;
860 u32 active_count;
861 u32 tu_size;
862 u32 active_frac;
863 u32 watermark;
864
865 s32 hblank_sym;
866 s32 vblank_sym;
867
868 /* Training data */
869 u32 drive_current;
870 u32 preemphasis;
871 u32 postcursor;
Simon Glassdedc44b2015-04-14 21:03:44 -0600872 u8 aux_rd_interval;
873 u8 tps3_supported;
Simon Glass00f37322015-04-14 21:03:40 -0600874};
875
876struct tegra_dc_sor_data {
877 void *base;
878 void *pmc_base;
879 u8 portnum; /* 0 or 1 */
880 int power_is_up;
881};
882
883#define TEGRA_SOR_TIMEOUT_MS 1000
884#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000
885
886int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
887 const struct tegra_dp_link_config *link_cfg);
888int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd);
889void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
890 u8 training_pattern, const struct tegra_dp_link_config *link_cfg);
891void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw);
892void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count);
893void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
894 int power_up);
895void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int);
896void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
897 u8 *lane_count);
898void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
899 const struct tegra_dp_link_config *link_cfg);
900void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
901 const struct tegra_dp_link_config *link_cfg);
Simon Glassdedc44b2015-04-14 21:03:44 -0600902int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor,
903 const struct tegra_dp_link_config *link_cfg);
904int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor,
905 const struct tegra_dp_link_config *cfg);
906void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor);
907void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,
908 u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported);
Simon Glass00f37322015-04-14 21:03:40 -0600909
910int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
911 const struct tegra_dp_link_config *link_cfg,
912 const struct display_timing *timing);
Simon Glassdedc44b2015-04-14 21:03:44 -0600913int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor);
914
915void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
916 int *dc_reg_ctx);
917int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl);
918void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
919 int *dc_reg_ctx);
920
Simon Glass00f37322015-04-14 21:03:40 -0600921int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp);
922#endif