blob: 013e40e3b9c200aa896ca5db8d77c6cab0bfab30 [file] [log] [blame]
wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf4675562002-10-02 14:20:15 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf4675562002-10-02 14:20:15 +000026#ifdef CONFIG_LCD /* with LCD controller ? */
Jeroen Hofstee59155f42013-01-22 10:44:09 +000027#define CONFIG_MPC8XX_LCD
Wolfgang Denk21f971e2008-07-07 01:22:29 +020028#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
29#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk27b207f2003-07-24 23:38:38 +000030#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000031#endif
32
33#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020034#define CONFIG_SYS_SMC_RXBUFLEN 128
35#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000036#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000037
wdenkae3af052003-08-07 22:18:11 +000038#define CONFIG_BOOTCOUNT_LIMIT
39
40#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000041
42#define CONFIG_BOARD_TYPES 1 /* support board types */
43
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010044#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000045
46#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000047
48#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000049 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000050 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000052 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "addip=setenv bootargs ${bootargs} " \
54 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
55 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000056 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010057 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000058 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
60 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000061 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020062 "hostname=TQM823L\0" \
63 "bootfile=TQM823L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020064 "fdt_addr=40040000\0" \
65 "kernel_addr=40060000\0" \
66 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020067 "u-boot=TQM823L/u-image.bin\0" \
68 "load=tftp 200000 ${u-boot}\0" \
69 "update=prot off 40000000 +${filesize};" \
70 "era 40000000 +${filesize};" \
71 "cp.b 200000 40000000 ${filesize};" \
72 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000073 ""
74#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000075
76#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000078
79#undef CONFIG_WATCHDOG /* watchdog disabled */
80
wdenka522fa02004-01-04 22:51:12 +000081#if defined(CONFIG_LCD)
wdenkf4675562002-10-02 14:20:15 +000082# undef CONFIG_STATUS_LED /* disturbs display */
83#else
84# define CONFIG_STATUS_LED 1 /* Status LED enabled */
85#endif /* CONFIG_LCD */
86
wdenka522fa02004-01-04 22:51:12 +000087#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkf4675562002-10-02 14:20:15 +000088
Jon Loeliger37d4bb72007-07-09 21:38:02 -050089/*
90 * BOOTP options
91 */
92#define CONFIG_BOOTP_SUBNETMASK
93#define CONFIG_BOOTP_GATEWAY
94#define CONFIG_BOOTP_HOSTNAME
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_BOOTFILESIZE
97
wdenkf4675562002-10-02 14:20:15 +000098
99#define CONFIG_MAC_PARTITION
100#define CONFIG_DOS_PARTITION
101
102#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
103
Jon Loeliger26946902007-07-04 22:30:50 -0500104
105/*
106 * Command line configuration.
107 */
Jon Loeliger26946902007-07-04 22:30:50 -0500108#define CONFIG_CMD_ASKENV
109#define CONFIG_CMD_DATE
110#define CONFIG_CMD_DHCP
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100111#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500112#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200113#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500114#define CONFIG_CMD_SNTP
115
wdenk27b207f2003-07-24 23:38:38 +0000116#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger26946902007-07-04 22:30:50 -0500117 #define CONFIG_CMD_BMP
wdenk27b207f2003-07-24 23:38:38 +0000118#endif
wdenkf4675562002-10-02 14:20:15 +0000119
wdenkf4675562002-10-02 14:20:15 +0000120
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200121#define CONFIG_NETCONSOLE
122
wdenkf4675562002-10-02 14:20:15 +0000123/*
124 * Miscellaneous configurable options
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000127
Wolfgang Denk2751a952006-10-28 02:29:14 +0200128#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenk6aff3112002-12-17 01:51:00 +0000130
Jon Loeliger26946902007-07-04 22:30:50 -0500131#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000133#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000135#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
137#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
138#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
141#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000144
wdenkf4675562002-10-02 14:20:15 +0000145/*
146 * Low Level Configuration Settings
147 * (address mappings, register initial values, etc.)
148 * You should know what you are doing if you make changes here.
149 */
150/*-----------------------------------------------------------------------
151 * Internal Memory Mapped Register
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000154
155/*-----------------------------------------------------------------------
156 * Definitions for initial stack pointer and data area (in DPRAM)
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200159#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200160#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000162
163/*-----------------------------------------------------------------------
164 * Start addresses for the final memory configuration
165 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_SDRAM_BASE 0x00000000
169#define CONFIG_SYS_FLASH_BASE 0x40000000
170#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
172#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000173
174/*
175 * For booting Linux, the board info and command line data
176 * have to be in the first 8 MB of memory, since this is
177 * the maximum mapped by the Linux kernel during initialization.
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000180
181/*-----------------------------------------------------------------------
182 * FLASH organization
183 */
wdenkf4675562002-10-02 14:20:15 +0000184
Martin Krausee318d9e2007-09-27 11:10:08 +0200185/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200187#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
189#define CONFIG_SYS_FLASH_EMPTY_INFO
190#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
191#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
192#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000193
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200194#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200195#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
196#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000197
198/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200199#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
200#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200203
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200204#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
205
wdenkf4675562002-10-02 14:20:15 +0000206/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200207 * Dynamic MTD partition support
208 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100209#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200210#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
211#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200212#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
213
214#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
215 "128k(dtb)," \
216 "1664k(kernel)," \
217 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200218 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200219
220/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000221 * Hardware Information Block
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
224#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
225#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000226
227/*-----------------------------------------------------------------------
228 * Cache Configuration
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500231#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000233#endif
234
235/*-----------------------------------------------------------------------
236 * SYPCR - System Protection Control 11-9
237 * SYPCR can only be written once after reset!
238 *-----------------------------------------------------------------------
239 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
240 */
241#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000243 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
244#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000246#endif
247
248/*-----------------------------------------------------------------------
249 * SIUMCR - SIU Module Configuration 11-6
250 *-----------------------------------------------------------------------
251 * PCMCIA config., multi-function pin tri-state
252 */
253#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000255#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000257#endif /* CONFIG_CAN_DRIVER */
258
259/*-----------------------------------------------------------------------
260 * TBSCR - Time Base Status and Control 11-26
261 *-----------------------------------------------------------------------
262 * Clear Reference Interrupt Status, Timebase freezing enabled
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000265
266/*-----------------------------------------------------------------------
267 * RTCSC - Real-Time Clock Status and Control Register 11-27
268 *-----------------------------------------------------------------------
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000271
272/*-----------------------------------------------------------------------
273 * PISCR - Periodic Interrupt Status and Control 11-31
274 *-----------------------------------------------------------------------
275 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000278
279/*-----------------------------------------------------------------------
280 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
281 *-----------------------------------------------------------------------
282 * Reset PLL lock status sticky bit, timer expired status bit and timer
283 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000286
287/*-----------------------------------------------------------------------
288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
292 */
293#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000295 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
296 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000297
298/*-----------------------------------------------------------------------
299 * PCMCIA stuff
300 *-----------------------------------------------------------------------
301 *
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
304#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
305#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
306#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
307#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
308#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
309#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
310#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000311
312/*-----------------------------------------------------------------------
313 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
314 *-----------------------------------------------------------------------
315 */
316
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000317#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000318#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
319
320#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
321#undef CONFIG_IDE_LED /* LED for ide not supported */
322#undef CONFIG_IDE_RESET /* reset for ide not supported */
323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
325#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000330
331/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000333
334/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000336
337/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000339
340/*-----------------------------------------------------------------------
341 *
342 *-----------------------------------------------------------------------
343 *
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000346
347/*
348 * Init Memory Controller:
349 *
350 * BR0/1 and OR0/1 (FLASH)
351 */
352
353#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
354#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
355
356/* used to re-map FLASH both when starting from SRAM or FLASH:
357 * restrict access enough to keep SRAM working (if any)
358 * but not too much to meddle with FLASH accesses
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
361#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000362
363/*
364 * FLASH timing:
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000367 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
370#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
371#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
374#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
375#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000376
377/*
378 * BR2/3 and OR2/3 (SDRAM)
379 *
380 */
381#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
382#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
383#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
384
385/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
389#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000390
391#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
393#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000394#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
396#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
397#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
398#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000399 BR_PS_8 | BR_MS_UPMB | BR_V )
400#endif /* CONFIG_CAN_DRIVER */
401
402/*
403 * Memory Periodic Timer Prescaler
404 *
405 * The Divider for PTA (refresh timer) configuration is based on an
406 * example SDRAM configuration (64 MBit, one bank). The adjustment to
407 * the number of chip selects (NCS) and the actually needed refresh
408 * rate is done by setting MPTPR.
409 *
410 * PTA is calculated from
411 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
412 *
413 * gclk CPU clock (not bus clock!)
414 * Trefresh Refresh cycle * 4 (four word bursts used)
415 *
416 * 4096 Rows from SDRAM example configuration
417 * 1000 factor s -> ms
418 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
419 * 4 Number of refresh cycles per period
420 * 64 Refresh cycle in ms per number of rows
421 * --------------------------------------------
422 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
423 *
424 * 50 MHz => 50.000.000 / Divider = 98
425 * 66 Mhz => 66.000.000 / Divider = 129
426 * 80 Mhz => 80.000.000 / Divider = 156
427 */
wdenke9132ea2004-04-24 23:23:30 +0000428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
430#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000431
432/*
433 * For 16 MBit, refresh rates could be 31.3 us
434 * (= 64 ms / 2K = 125 / quad bursts).
435 * For a simpler initialization, 15.6 us is used instead.
436 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
438 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000439 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
441#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000442
443/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
445#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000446
447/*
448 * MAMR settings for SDRAM
449 */
450
451/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000453 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
454 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
455/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000457 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
458 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
459
Heiko Schocher7026ead2010-02-09 15:50:27 +0100460/* pass open firmware flat tree */
461#define CONFIG_OF_LIBFDT 1
462#define CONFIG_OF_BOARD_SETUP 1
463#define CONFIG_HWCONFIG 1
464
wdenkf4675562002-10-02 14:20:15 +0000465#endif /* __CONFIG_H */