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Masahiro Yamadafc26b7b2016-03-18 16:41:49 +09001/*
Masahiro Yamada52159d22016-10-07 16:43:00 +09002 * Device Tree Source for UniPhier LD11 SoC
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +09003 *
Masahiro Yamadac4adc502016-06-29 19:38:56 +09004 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +09006 *
7 * SPDX-License-Identifier: GPL-2.0+ X11
8 */
9
Masahiro Yamadacd622142016-12-05 18:31:39 +090010/memreserve/ 0x80000000 0x00080000;
Masahiro Yamadac4adc502016-06-29 19:38:56 +090011
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090012/ {
Masahiro Yamada52159d22016-10-07 16:43:00 +090013 compatible = "socionext,uniphier-ld11";
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090014 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
17
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
21
Masahiro Yamadac4adc502016-06-29 19:38:56 +090022 cpu-map {
23 cluster0 {
24 core0 {
25 cpu = <&cpu0>;
26 };
27 core1 {
28 cpu = <&cpu1>;
29 };
30 };
31 };
32
33 cpu0: cpu@0 {
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090034 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 reg = <0 0x000>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090037 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 operating-points-v2 = <&cluster0_opp>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090040 };
41
Masahiro Yamadac4adc502016-06-29 19:38:56 +090042 cpu1: cpu@1 {
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090043 device_type = "cpu";
44 compatible = "arm,cortex-a53", "arm,armv8";
45 reg = <0 0x001>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090046 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090049 };
50 };
51
Masahiro Yamadacd622142016-12-05 18:31:39 +090052 cluster0_opp: opp_table {
53 compatible = "operating-points-v2";
54 opp-shared;
55
56 opp@245000000 {
57 opp-hz = /bits/ 64 <245000000>;
58 clock-latency-ns = <300>;
59 };
60 opp@250000000 {
61 opp-hz = /bits/ 64 <250000000>;
62 clock-latency-ns = <300>;
63 };
64 opp@490000000 {
65 opp-hz = /bits/ 64 <490000000>;
66 clock-latency-ns = <300>;
67 };
68 opp@500000000 {
69 opp-hz = /bits/ 64 <500000000>;
70 clock-latency-ns = <300>;
71 };
72 opp@653334000 {
73 opp-hz = /bits/ 64 <653334000>;
74 clock-latency-ns = <300>;
75 };
76 opp@666667000 {
77 opp-hz = /bits/ 64 <666667000>;
78 clock-latency-ns = <300>;
79 };
80 opp@980000000 {
81 opp-hz = /bits/ 64 <980000000>;
82 clock-latency-ns = <300>;
83 };
84 };
85
86 psci {
87 compatible = "arm,psci-1.0";
88 method = "smc";
89 };
90
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090091 clocks {
Masahiro Yamadac4adc502016-06-29 19:38:56 +090092 refclk: ref {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <25000000>;
96 };
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +090097 };
98
99 timer {
100 compatible = "arm,armv8-timer";
Masahiro Yamada35343a22016-09-22 07:42:23 +0900101 interrupts = <1 13 4>,
102 <1 14 4>,
103 <1 11 4>,
104 <1 10 4>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900105 };
106
Masahiro Yamada7ad79c12017-03-13 00:16:40 +0900107 soc@0 {
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900108 compatible = "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges = <0 0 0 0xffffffff>;
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900112 u-boot,dm-pre-reloc;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900113
114 serial0: serial@54006800 {
115 compatible = "socionext,uniphier-uart";
116 status = "disabled";
117 reg = <0x54006800 0x40>;
118 interrupts = <0 33 4>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart0>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900121 clocks = <&peri_clk 0>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900122 clock-frequency = <58820000>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900123 };
124
125 serial1: serial@54006900 {
126 compatible = "socionext,uniphier-uart";
127 status = "disabled";
128 reg = <0x54006900 0x40>;
129 interrupts = <0 35 4>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart1>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900132 clocks = <&peri_clk 1>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900133 clock-frequency = <58820000>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900134 };
135
136 serial2: serial@54006a00 {
137 compatible = "socionext,uniphier-uart";
138 status = "disabled";
139 reg = <0x54006a00 0x40>;
140 interrupts = <0 37 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart2>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900143 clocks = <&peri_clk 2>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900144 clock-frequency = <58820000>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900145 };
146
147 serial3: serial@54006b00 {
148 compatible = "socionext,uniphier-uart";
149 status = "disabled";
150 reg = <0x54006b00 0x40>;
151 interrupts = <0 177 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_uart3>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900154 clocks = <&peri_clk 3>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900155 clock-frequency = <58820000>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900156 };
157
158 i2c0: i2c@58780000 {
159 compatible = "socionext,uniphier-fi2c";
160 status = "disabled";
161 reg = <0x58780000 0x80>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 interrupts = <0 41 4>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c0>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900167 clocks = <&peri_clk 4>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900168 clock-frequency = <100000>;
169 };
170
171 i2c1: i2c@58781000 {
172 compatible = "socionext,uniphier-fi2c";
173 status = "disabled";
174 reg = <0x58781000 0x80>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 interrupts = <0 42 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c1>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900180 clocks = <&peri_clk 5>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900181 clock-frequency = <100000>;
182 };
183
184 i2c2: i2c@58782000 {
185 compatible = "socionext,uniphier-fi2c";
186 reg = <0x58782000 0x80>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 interrupts = <0 43 4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900190 clocks = <&peri_clk 6>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900191 clock-frequency = <400000>;
192 };
193
194 i2c3: i2c@58783000 {
195 compatible = "socionext,uniphier-fi2c";
196 status = "disabled";
197 reg = <0x58783000 0x80>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200 interrupts = <0 44 4>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c3>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900203 clocks = <&peri_clk 7>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900204 clock-frequency = <100000>;
205 };
206
207 i2c4: i2c@58784000 {
208 compatible = "socionext,uniphier-fi2c";
209 status = "disabled";
210 reg = <0x58784000 0x80>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 interrupts = <0 45 4>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900216 clocks = <&peri_clk 8>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900217 clock-frequency = <100000>;
218 };
219
220 i2c5: i2c@58785000 {
221 compatible = "socionext,uniphier-fi2c";
222 reg = <0x58785000 0x80>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 interrupts = <0 25 4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900226 clocks = <&peri_clk 9>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900227 clock-frequency = <400000>;
228 };
229
230 system_bus: system-bus@58c00000 {
231 compatible = "socionext,uniphier-system-bus";
232 status = "disabled";
233 reg = <0x58c00000 0x400>;
234 #address-cells = <2>;
235 #size-cells = <1>;
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_system_bus>;
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900238 };
239
240 smpctrl@59800000 {
241 compatible = "socionext,uniphier-smpctrl";
242 reg = <0x59801000 0x400>;
243 };
244
Masahiro Yamadacd622142016-12-05 18:31:39 +0900245 sdctrl@59810000 {
246 compatible = "socionext,uniphier-ld11-sdctrl",
247 "simple-mfd", "syscon";
248 reg = <0x59810000 0x400>;
249
250 sd_rst: reset {
251 compatible = "socionext,uniphier-ld11-sd-reset";
252 #reset-cells = <1>;
253 };
254 };
255
Masahiro Yamada35343a22016-09-22 07:42:23 +0900256 perictrl@59820000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900257 compatible = "socionext,uniphier-ld11-perictrl",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900258 "simple-mfd", "syscon";
259 reg = <0x59820000 0x200>;
260
261 peri_clk: clock {
262 compatible = "socionext,uniphier-ld11-peri-clock";
263 #clock-cells = <1>;
264 };
265
266 peri_rst: reset {
267 compatible = "socionext,uniphier-ld11-peri-reset";
268 #reset-cells = <1>;
269 };
270 };
271
Masahiro Yamadacd622142016-12-05 18:31:39 +0900272 emmc: sdhc@5a000000 {
Masahiro Yamada7a6139c2017-01-04 20:08:37 +0900273 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
Masahiro Yamadacd622142016-12-05 18:31:39 +0900274 reg = <0x5a000000 0x400>;
275 interrupts = <0 78 4>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_emmc_1v8>;
278 clocks = <&sys_clk 4>;
279 bus-width = <8>;
280 mmc-ddr-1_8v;
281 mmc-hs200-1_8v;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900282 };
283
Masahiro Yamadad7e103c2016-05-24 21:14:03 +0900284 usb0: usb@5a800100 {
285 compatible = "socionext,uniphier-ehci", "generic-ehci";
286 status = "disabled";
287 reg = <0x5a800100 0x100>;
288 interrupts = <0 243 4>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_usb0>;
Masahiro Yamada52159d22016-10-07 16:43:00 +0900291 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
292 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
293 <&mio_rst 12>;
Masahiro Yamadad7e103c2016-05-24 21:14:03 +0900294 };
295
296 usb1: usb@5a810100 {
297 compatible = "socionext,uniphier-ehci", "generic-ehci";
298 status = "disabled";
299 reg = <0x5a810100 0x100>;
300 interrupts = <0 244 4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usb1>;
Masahiro Yamada52159d22016-10-07 16:43:00 +0900303 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
304 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
305 <&mio_rst 13>;
Masahiro Yamadad7e103c2016-05-24 21:14:03 +0900306 };
307
308 usb2: usb@5a820100 {
309 compatible = "socionext,uniphier-ehci", "generic-ehci";
310 status = "disabled";
311 reg = <0x5a820100 0x100>;
312 interrupts = <0 245 4>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_usb2>;
Masahiro Yamada52159d22016-10-07 16:43:00 +0900315 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
316 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
317 <&mio_rst 14>;
Masahiro Yamadad7e103c2016-05-24 21:14:03 +0900318 };
319
Masahiro Yamada35343a22016-09-22 07:42:23 +0900320 mioctrl@5b3e0000 {
Masahiro Yamada7317a942017-03-13 00:16:41 +0900321 compatible = "socionext,uniphier-ld11-mioctrl",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900322 "simple-mfd", "syscon";
Masahiro Yamadad7e103c2016-05-24 21:14:03 +0900323 reg = <0x5b3e0000 0x800>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900324
325 mio_clk: clock {
326 compatible = "socionext,uniphier-ld11-mio-clock";
327 #clock-cells = <1>;
328 };
329
330 mio_rst: reset {
331 compatible = "socionext,uniphier-ld11-mio-reset";
332 #reset-cells = <1>;
333 resets = <&sys_rst 7>;
334 };
Masahiro Yamadad7e103c2016-05-24 21:14:03 +0900335 };
336
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900337 soc-glue@5f800000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900338 compatible = "socionext,uniphier-ld11-soc-glue",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900339 "simple-mfd", "syscon";
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900340 reg = <0x5f800000 0x2000>;
341 u-boot,dm-pre-reloc;
342
343 pinctrl: pinctrl {
344 compatible = "socionext,uniphier-ld11-pinctrl";
345 u-boot,dm-pre-reloc;
346 };
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900347 };
348
Masahiro Yamada1013aef2016-06-29 19:39:02 +0900349 aidet@5fc20000 {
350 compatible = "simple-mfd", "syscon";
351 reg = <0x5fc20000 0x200>;
352 };
353
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900354 gic: interrupt-controller@5fe00000 {
355 compatible = "arm,gic-v3";
356 reg = <0x5fe00000 0x10000>, /* GICD */
357 <0x5fe40000 0x80000>; /* GICR */
358 interrupt-controller;
359 #interrupt-cells = <3>;
360 interrupts = <1 9 4>;
361 };
Masahiro Yamada35343a22016-09-22 07:42:23 +0900362
363 sysctrl@61840000 {
364 compatible = "socionext,uniphier-ld11-sysctrl",
365 "simple-mfd", "syscon";
Masahiro Yamadacd622142016-12-05 18:31:39 +0900366 reg = <0x61840000 0x10000>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900367
368 sys_clk: clock {
369 compatible = "socionext,uniphier-ld11-clock";
370 #clock-cells = <1>;
371 };
372
373 sys_rst: reset {
374 compatible = "socionext,uniphier-ld11-reset";
375 #reset-cells = <1>;
376 };
377 };
Masahiro Yamadacd622142016-12-05 18:31:39 +0900378
379 nand: nand@68000000 {
380 compatible = "socionext,denali-nand-v5b";
381 status = "disabled";
382 reg-names = "nand_data", "denali_reg";
383 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
384 interrupts = <0 65 4>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_nand>;
387 clocks = <&sys_clk 2>;
388 nand-ecc-strength = <8>;
389 };
Masahiro Yamadafc26b7b2016-03-18 16:41:49 +0900390 };
391};
392
393/include/ "uniphier-pinctrl.dtsi"