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Shaohui Xie02b5d2e2015-11-11 17:58:37 +08001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1043AQDS_H__
8#define __LS1043AQDS_H__
9
10#include "ls1043a_common.h"
11
12#define CONFIG_DISPLAY_CPUINFO
Qianyu Gongb0f20ca2016-01-25 15:16:07 +080013#ifdef CONFIG_QSPI_BOOT
14#define CONFIG_DISPLAY_BOARDINFO_LATE
15#else
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080016#define CONFIG_DISPLAY_BOARDINFO
Qianyu Gongb0f20ca2016-01-25 15:16:07 +080017#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080018
19#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
20#define CONFIG_SYS_TEXT_BASE 0x82000000
Qianyu Gongb0f20ca2016-01-25 15:16:07 +080021#elif defined(CONFIG_QSPI_BOOT)
22#define CONFIG_SYS_TEXT_BASE 0x40010000
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080023#else
24#define CONFIG_SYS_TEXT_BASE 0x60100000
25#endif
26
27#ifndef __ASSEMBLY__
28unsigned long get_board_sys_clk(void);
29unsigned long get_board_ddr_clk(void);
30#endif
31
32#define CONFIG_SYS_CLK_FREQ 100000000
33#define CONFIG_DDR_CLK_FREQ 100000000
34
35#define CONFIG_SKIP_LOWLEVEL_INIT
36
37#define CONFIG_LAYERSCAPE_NS_ACCESS
38
39#define CONFIG_DIMM_SLOTS_PER_CTLR 1
40/* Physical Memory Map */
41#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Shaohui Xie58e4ad12016-01-04 11:03:44 +080042#define CONFIG_NR_DRAM_BANKS 2
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080043
44#define CONFIG_DDR_SPD
45#define SPD_EEPROM_ADDRESS 0x51
46#define CONFIG_SYS_SPD_BUS_NUM 0
47
48#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
49#ifndef CONFIG_SYS_FSL_DDR4
50#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
51#endif
52
53#define CONFIG_DDR_ECC
54#ifdef CONFIG_DDR_ECC
55#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
56#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
57#endif
58
59#define CONFIG_SYS_HAS_SERDES
60
61#ifdef CONFIG_SYS_DPAA_FMAN
62#define CONFIG_FMAN_ENET
63#define CONFIG_PHYLIB
64#define CONFIG_PHY_VITESSE
65#define CONFIG_PHY_REALTEK
66#define CONFIG_PHYLIB_10G
67#define RGMII_PHY1_ADDR 0x1
68#define RGMII_PHY2_ADDR 0x2
69#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
70#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
71#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
72#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
73/* PHY address on QSGMII riser card on slot 1 */
74#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
75#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
76#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
77#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
78/* PHY address on QSGMII riser card on slot 2 */
79#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
80#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
81#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
82#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
83#endif
84
85#ifdef CONFIG_RAMBOOT_PBL
86#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
87#endif
88
89#ifdef CONFIG_NAND_BOOT
90#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
91#endif
92
93#ifdef CONFIG_SD_BOOT
Gong Qianyu166ef1e2016-01-25 15:16:06 +080094#ifdef CONFIG_SD_BOOT_QSPI
95#define CONFIG_SYS_FSL_PBL_RCW \
96 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
97#else
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080098#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
99#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800100#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800101
Wenbin Song2970e142016-01-21 17:14:55 +0800102/* LPUART */
103#ifdef CONFIG_LPUART
104#define CONFIG_LPUART_32B_REG
105#endif
106
Tang Yuantian989c5f02015-12-09 15:32:18 +0800107/* SATA */
108#define CONFIG_LIBATA
109#define CONFIG_SCSI_AHCI
110#define CONFIG_SCSI_AHCI_PLAT
111#define CONFIG_CMD_SCSI
112#define CONFIG_CMD_FAT
113#define CONFIG_CMD_EXT2
114#define CONFIG_DOS_PARTITION
115#define CONFIG_BOARD_LATE_INIT
116
117#define CONFIG_SYS_SATA AHCI_BASE_ADDR
118
119#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
120#define CONFIG_SYS_SCSI_MAX_LUN 1
121#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
122 CONFIG_SYS_SCSI_MAX_LUN)
123
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800124/*
125 * IFC Definitions
126 */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800127#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800128#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
129#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
130 CSPR_PORT_SIZE_16 | \
131 CSPR_MSEL_NOR | \
132 CSPR_V)
133#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
134#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
135 + 0x8000000) | \
136 CSPR_PORT_SIZE_16 | \
137 CSPR_MSEL_NOR | \
138 CSPR_V)
139#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
140
141#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
142 CSOR_NOR_TRHZ_80)
143#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
144 FTIM0_NOR_TEADC(0x5) | \
145 FTIM0_NOR_TEAHC(0x5))
146#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
147 FTIM1_NOR_TRAD_NOR(0x1a) | \
148 FTIM1_NOR_TSEQRAD_NOR(0x13))
149#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
150 FTIM2_NOR_TCH(0x4) | \
151 FTIM2_NOR_TWPH(0xe) | \
152 FTIM2_NOR_TWP(0x1c))
153#define CONFIG_SYS_NOR_FTIM3 0
154
155#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
156#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
157#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
158#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
159
160#define CONFIG_SYS_FLASH_EMPTY_INFO
161#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
162 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
163
164#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
165#define CONFIG_SYS_WRITE_SWAPPED_DATA
166
167/*
168 * NAND Flash Definitions
169 */
170#define CONFIG_NAND_FSL_IFC
171
172#define CONFIG_SYS_NAND_BASE 0x7e800000
173#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
174
175#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
176
177#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
178 | CSPR_PORT_SIZE_8 \
179 | CSPR_MSEL_NAND \
180 | CSPR_V)
181#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
182#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
183 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
184 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
185 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
186 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
187 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
188 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
189
190#define CONFIG_SYS_NAND_ONFI_DETECTION
191
192#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
193 FTIM0_NAND_TWP(0x18) | \
194 FTIM0_NAND_TWCHT(0x7) | \
195 FTIM0_NAND_TWH(0xa))
196#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
197 FTIM1_NAND_TWBE(0x39) | \
198 FTIM1_NAND_TRR(0xe) | \
199 FTIM1_NAND_TRP(0x18))
200#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
201 FTIM2_NAND_TREH(0xa) | \
202 FTIM2_NAND_TWHRE(0x1e))
203#define CONFIG_SYS_NAND_FTIM3 0x0
204
205#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
206#define CONFIG_SYS_MAX_NAND_DEVICE 1
207#define CONFIG_MTD_NAND_VERIFY_WRITE
208#define CONFIG_CMD_NAND
209
210#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800211#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800212
213#ifdef CONFIG_NAND_BOOT
214#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
215#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
216#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
217#endif
218
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800219#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800220#define CONFIG_QIXIS_I2C_ACCESS
221#define CONFIG_SYS_NO_FLASH
222#undef CONFIG_CMD_IMLS
223#endif
224
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800225/*
226 * QIXIS Definitions
227 */
228#define CONFIG_FSL_QIXIS
229
230#ifdef CONFIG_FSL_QIXIS
231#define QIXIS_BASE 0x7fb00000
232#define QIXIS_BASE_PHYS QIXIS_BASE
233#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
234#define QIXIS_LBMAP_SWITCH 6
235#define QIXIS_LBMAP_MASK 0x0f
236#define QIXIS_LBMAP_SHIFT 0
237#define QIXIS_LBMAP_DFLTBANK 0x00
238#define QIXIS_LBMAP_ALTBANK 0x04
Gong Qianyuee2a4ee2015-12-31 18:29:04 +0800239#define QIXIS_LBMAP_NAND 0x09
240#define QIXIS_LBMAP_SD 0x00
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800241#define QIXIS_LBMAP_SD_QSPI 0xff
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800242#define QIXIS_LBMAP_QSPI 0xff
Gong Qianyuee2a4ee2015-12-31 18:29:04 +0800243#define QIXIS_RCW_SRC_NAND 0x106
244#define QIXIS_RCW_SRC_SD 0x040
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800245#define QIXIS_RCW_SRC_QSPI 0x045
Gong Qianyua4b7d682015-12-31 18:29:03 +0800246#define QIXIS_RST_CTL_RESET 0x41
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800247#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
248#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
249#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
250
251#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
252#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
253 CSPR_PORT_SIZE_8 | \
254 CSPR_MSEL_GPCM | \
255 CSPR_V)
256#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
257#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
258 CSOR_NOR_NOR_MODE_AVD_NOR | \
259 CSOR_NOR_TRHZ_80)
260
261/*
262 * QIXIS Timing parameters for IFC GPCM
263 */
264#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
265 FTIM0_GPCM_TEADC(0x20) | \
266 FTIM0_GPCM_TEAHC(0x10))
267#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
268 FTIM1_GPCM_TRAD(0x1f))
269#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
270 FTIM2_GPCM_TCH(0x8) | \
271 FTIM2_GPCM_TWP(0xf0))
272#define CONFIG_SYS_FPGA_FTIM3 0x0
273#endif
274
275#ifdef CONFIG_NAND_BOOT
276#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
277#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
278#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
279#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
280#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
281#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
282#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
283#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
284#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
285#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
286#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
287#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
288#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
289#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
290#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
291#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
292#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
293#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
294#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
295#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
296#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
297#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
298#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
299#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
300#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
301#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
302#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
303#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
304#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
305#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
306#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
307#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
308#else
309#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
310#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
311#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
312#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
313#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
314#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
315#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
316#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
317#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
318#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
319#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
320#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
321#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
322#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
323#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
324#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
325#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
326#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
327#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
328#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
329#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
330#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
331#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
332#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
333#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
334#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
335#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
336#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
337#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
338#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
339#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
340#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
341#endif
342
343/*
344 * I2C bus multiplexer
345 */
346#define I2C_MUX_PCA_ADDR_PRI 0x77
347#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
348#define I2C_RETIMER_ADDR 0x18
349#define I2C_MUX_CH_DEFAULT 0x8
350#define I2C_MUX_CH_CH7301 0xC
351#define I2C_MUX_CH5 0xD
352#define I2C_MUX_CH7 0xF
353
354#define I2C_MUX_CH_VOL_MONITOR 0xa
355
356/* Voltage monitor on channel 2*/
357#define I2C_VOL_MONITOR_ADDR 0x40
358#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
359#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
360#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
361
362#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
363#ifndef CONFIG_SPL_BUILD
364#define CONFIG_VID
365#endif
366#define CONFIG_VOL_MONITOR_IR36021_SET
367#define CONFIG_VOL_MONITOR_INA220
368/* The lowest and highest voltage allowed for LS1043AQDS */
369#define VDD_MV_MIN 819
370#define VDD_MV_MAX 1212
371
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800372/* QSPI device */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800373#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800374#define CONFIG_FSL_QSPI
375#ifdef CONFIG_FSL_QSPI
376#define CONFIG_SPI_FLASH_SPANSION
377#define FSL_QSPI_FLASH_SIZE (1 << 24)
378#define FSL_QSPI_FLASH_NUM 2
379#endif
380#endif
381
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800382/*
383 * Miscellaneous configurable options
384 */
385#define CONFIG_MISC_INIT_R
386#define CONFIG_SYS_LONGHELP /* undef to save memory */
387#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
388#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
389#define CONFIG_SYS_PROMPT "=> "
390#define CONFIG_AUTO_COMPLETE
391#define CONFIG_SYS_PBSIZE \
392 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
393#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
394
395#define CONFIG_CMD_GREPENV
396#define CONFIG_CMD_MEMINFO
397#define CONFIG_CMD_MEMTEST
398#define CONFIG_SYS_MEMTEST_START 0x80000000
399#define CONFIG_SYS_MEMTEST_END 0x9fffffff
400
401#define CONFIG_SYS_HZ 1000
402
403/*
404 * Stack sizes
405 * The stack sizes are set up in start.S using the settings below
406 */
407#define CONFIG_STACKSIZE (30 * 1024)
408
409#define CONFIG_SYS_INIT_SP_OFFSET \
410 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
411
412#ifdef CONFIG_SPL_BUILD
413#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
414#else
415#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
416#endif
417
418/*
419 * Environment
420 */
421#define CONFIG_ENV_OVERWRITE
422
423#ifdef CONFIG_NAND_BOOT
424#define CONFIG_ENV_IS_IN_NAND
425#define CONFIG_ENV_SIZE 0x2000
426#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
427#elif defined(CONFIG_SD_BOOT)
428#define CONFIG_ENV_OFFSET (1024 * 1024)
429#define CONFIG_ENV_IS_IN_MMC
430#define CONFIG_SYS_MMC_ENV_DEV 0
431#define CONFIG_ENV_SIZE 0x2000
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800432#elif defined(CONFIG_QSPI_BOOT)
433#define CONFIG_ENV_IS_IN_SPI_FLASH
434#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
435#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
436#define CONFIG_ENV_SECT_SIZE 0x10000
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800437#else
438#define CONFIG_ENV_IS_IN_FLASH
439#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
440#define CONFIG_ENV_SECT_SIZE 0x20000
441#define CONFIG_ENV_SIZE 0x20000
442#endif
443
444#define CONFIG_OF_LIBFDT
445#define CONFIG_OF_BOARD_SETUP
446#define CONFIG_CMD_BOOTZ
447#define CONFIG_CMD_MII
448#define CONFIG_CMDLINE_TAG
449
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530450#include <asm/fsl_secure_boot.h>
451
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800452#endif /* __LS1043AQDS_H__ */