blob: fd559e05fc7f4b3bff2cb2f8dac049053cf2c709 [file] [log] [blame]
Stefan Roeseb113c9b2020-07-30 13:56:16 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Stefan Roese <sr@denx.de>
4 */
5
6#include <clk-uclass.h>
7#include <dm.h>
8#include <dt-bindings/clock/octeon-clock.h>
9
10DECLARE_GLOBAL_DATA_PTR;
11
12struct octeon_clk_priv {
13 u64 core_clk;
14 u64 io_clk;
15};
16
17static int octeon_clk_enable(struct clk *clk)
18{
19 /* Nothing to do on Octeon */
20 return 0;
21}
22
23static ulong octeon_clk_get_rate(struct clk *clk)
24{
25 struct octeon_clk_priv *priv = dev_get_priv(clk->dev);
26
27 switch (clk->id) {
28 case OCTEON_CLK_CORE:
29 return priv->core_clk;
30
31 case OCTEON_CLK_IO:
32 return priv->io_clk;
33
34 default:
35 return 0;
36 }
37
38 return 0;
39}
40
41static struct clk_ops octeon_clk_ops = {
42 .enable = octeon_clk_enable,
43 .get_rate = octeon_clk_get_rate,
44};
45
46static const struct udevice_id octeon_clk_ids[] = {
47 { .compatible = "mrvl,octeon-clk" },
48 { /* sentinel */ }
49};
50
51static int octeon_clk_probe(struct udevice *dev)
52{
53 struct octeon_clk_priv *priv = dev_get_priv(dev);
54
55 /*
56 * The clock values are already read into GD, lets just store them
57 * in priv data
58 */
59 priv->core_clk = gd->cpu_clk;
60 priv->io_clk = gd->bus_clk;
61
62 return 0;
63}
64
65U_BOOT_DRIVER(clk_octeon) = {
66 .name = "clk_octeon",
67 .id = UCLASS_CLK,
68 .of_match = octeon_clk_ids,
69 .ops = &octeon_clk_ops,
70 .probe = octeon_clk_probe,
71 .priv_auto_alloc_size = sizeof(struct octeon_clk_priv),
72};