blob: 186ab19d35ef2f0b42c9a2e8cb2b87f1071684db [file] [log] [blame]
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#include <common.h>
19
20#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII))
21
22/*
23 * The u-boot networking stack is a little weird. It seems like the
24 * networking core allocates receive buffers up front without any
25 * regard to the hardware that's supposed to actually receive those
26 * packets.
27 *
28 * The MACB receives packets into 128-byte receive buffers, so the
29 * buffers allocated by the core isn't very practical to use. We'll
30 * allocate our own, but we need one such buffer in case a packet
31 * wraps around the DMA ring so that we have to copy it.
32 *
33 * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific
34 * configuration header. This way, the core allocates one RX buffer
35 * and one TX buffer, each of which can hold a ethernet packet of
36 * maximum size.
37 *
38 * For some reason, the networking core unconditionally specifies a
39 * 32-byte packet "alignment" (which really should be called
40 * "padding"). MACB shouldn't need that, but we'll refrain from any
41 * core modifications here...
42 */
43
44#include <net.h>
45#include <malloc.h>
46
47#include <linux/mii.h>
48#include <asm/io.h>
49#include <asm/dma-mapping.h>
50#include <asm/arch/clk.h>
51
52#include "macb.h"
53
54#define CFG_MACB_RX_BUFFER_SIZE 4096
55#define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128)
56#define CFG_MACB_TX_RING_SIZE 16
57#define CFG_MACB_TX_TIMEOUT 1000
58#define CFG_MACB_AUTONEG_TIMEOUT 5000000
59
60struct macb_dma_desc {
61 u32 addr;
62 u32 ctrl;
63};
64
65#define RXADDR_USED 0x00000001
66#define RXADDR_WRAP 0x00000002
67
68#define RXBUF_FRMLEN_MASK 0x00000fff
69#define RXBUF_FRAME_START 0x00004000
70#define RXBUF_FRAME_END 0x00008000
71#define RXBUF_TYPEID_MATCH 0x00400000
72#define RXBUF_ADDR4_MATCH 0x00800000
73#define RXBUF_ADDR3_MATCH 0x01000000
74#define RXBUF_ADDR2_MATCH 0x02000000
75#define RXBUF_ADDR1_MATCH 0x04000000
76#define RXBUF_BROADCAST 0x80000000
77
78#define TXBUF_FRMLEN_MASK 0x000007ff
79#define TXBUF_FRAME_END 0x00008000
80#define TXBUF_NOCRC 0x00010000
81#define TXBUF_EXHAUSTED 0x08000000
82#define TXBUF_UNDERRUN 0x10000000
83#define TXBUF_MAXRETRY 0x20000000
84#define TXBUF_WRAP 0x40000000
85#define TXBUF_USED 0x80000000
86
87struct macb_device {
88 void *regs;
89
90 unsigned int rx_tail;
91 unsigned int tx_head;
92 unsigned int tx_tail;
93
94 void *rx_buffer;
95 void *tx_buffer;
96 struct macb_dma_desc *rx_ring;
97 struct macb_dma_desc *tx_ring;
98
99 unsigned long rx_buffer_dma;
100 unsigned long rx_ring_dma;
101 unsigned long tx_ring_dma;
102
103 const struct device *dev;
104 struct eth_device netdev;
105 unsigned short phy_addr;
106};
107#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
108
109static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
110{
111 unsigned long netctl;
112 unsigned long netstat;
113 unsigned long frame;
114
115 netctl = macb_readl(macb, NCR);
116 netctl |= MACB_BIT(MPE);
117 macb_writel(macb, NCR, netctl);
118
119 frame = (MACB_BF(SOF, 1)
120 | MACB_BF(RW, 1)
121 | MACB_BF(PHYA, macb->phy_addr)
122 | MACB_BF(REGA, reg)
123 | MACB_BF(CODE, 2)
124 | MACB_BF(DATA, value));
125 macb_writel(macb, MAN, frame);
126
127 do {
128 netstat = macb_readl(macb, NSR);
129 } while (!(netstat & MACB_BIT(IDLE)));
130
131 netctl = macb_readl(macb, NCR);
132 netctl &= ~MACB_BIT(MPE);
133 macb_writel(macb, NCR, netctl);
134}
135
136static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
137{
138 unsigned long netctl;
139 unsigned long netstat;
140 unsigned long frame;
141
142 netctl = macb_readl(macb, NCR);
143 netctl |= MACB_BIT(MPE);
144 macb_writel(macb, NCR, netctl);
145
146 frame = (MACB_BF(SOF, 1)
147 | MACB_BF(RW, 2)
148 | MACB_BF(PHYA, macb->phy_addr)
149 | MACB_BF(REGA, reg)
150 | MACB_BF(CODE, 2));
151 macb_writel(macb, MAN, frame);
152
153 do {
154 netstat = macb_readl(macb, NSR);
155 } while (!(netstat & MACB_BIT(IDLE)));
156
157 frame = macb_readl(macb, MAN);
158
159 netctl = macb_readl(macb, NCR);
160 netctl &= ~MACB_BIT(MPE);
161 macb_writel(macb, NCR, netctl);
162
163 return MACB_BFEXT(DATA, frame);
164}
165
166#if (CONFIG_COMMANDS & CFG_CMD_NET)
167
168static int macb_send(struct eth_device *netdev, volatile void *packet,
169 int length)
170{
171 struct macb_device *macb = to_macb(netdev);
172 unsigned long paddr, ctrl;
173 unsigned int tx_head = macb->tx_head;
174 int i;
175
176 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
177
178 ctrl = length & TXBUF_FRMLEN_MASK;
179 ctrl |= TXBUF_FRAME_END;
180 if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) {
181 ctrl |= TXBUF_WRAP;
182 macb->tx_head = 0;
183 } else
184 macb->tx_head++;
185
186 macb->tx_ring[tx_head].ctrl = ctrl;
187 macb->tx_ring[tx_head].addr = paddr;
188 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
189
190 /*
191 * I guess this is necessary because the networking core may
192 * re-use the transmit buffer as soon as we return...
193 */
194 i = 0;
195 while (!(macb->tx_ring[tx_head].ctrl & TXBUF_USED)) {
196 if (i > CFG_MACB_TX_TIMEOUT) {
197 printf("%s: TX timeout\n", netdev->name);
198 break;
199 }
200 udelay(1);
201 i++;
202 }
203
204 dma_unmap_single(packet, length, paddr);
205
206 if (i <= CFG_MACB_TX_TIMEOUT) {
207 ctrl = macb->tx_ring[tx_head].ctrl;
208 if (ctrl & TXBUF_UNDERRUN)
209 printf("%s: TX underrun\n", netdev->name);
210 if (ctrl & TXBUF_EXHAUSTED)
211 printf("%s: TX buffers exhausted in mid frame\n",
212 netdev->name);
213 }
214
215 /* No one cares anyway */
216 return 0;
217}
218
219static void reclaim_rx_buffers(struct macb_device *macb,
220 unsigned int new_tail)
221{
222 unsigned int i;
223
224 i = macb->rx_tail;
225 while (i > new_tail) {
226 macb->rx_ring[i].addr &= ~RXADDR_USED;
227 i++;
228 if (i > CFG_MACB_RX_RING_SIZE)
229 i = 0;
230 }
231
232 while (i < new_tail) {
233 macb->rx_ring[i].addr &= ~RXADDR_USED;
234 i++;
235 }
236
237 macb->rx_tail = new_tail;
238}
239
240static int macb_recv(struct eth_device *netdev)
241{
242 struct macb_device *macb = to_macb(netdev);
243 unsigned int rx_tail = macb->rx_tail;
244 void *buffer;
245 int length;
246 int wrapped = 0;
247 u32 status;
248
249 for (;;) {
250 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
251 return -1;
252
253 status = macb->rx_ring[rx_tail].ctrl;
254 if (status & RXBUF_FRAME_START) {
255 if (rx_tail != macb->rx_tail)
256 reclaim_rx_buffers(macb, rx_tail);
257 wrapped = 0;
258 }
259
260 if (status & RXBUF_FRAME_END) {
261 buffer = macb->rx_buffer + 128 * macb->rx_tail;
262 length = status & RXBUF_FRMLEN_MASK;
263 if (wrapped) {
264 unsigned int headlen, taillen;
265
266 headlen = 128 * (CFG_MACB_RX_RING_SIZE
267 - macb->rx_tail);
268 taillen = length - headlen;
269 memcpy((void *)NetRxPackets[0],
270 buffer, headlen);
271 memcpy((void *)NetRxPackets[0] + headlen,
272 macb->rx_buffer, taillen);
273 buffer = (void *)NetRxPackets[0];
274 }
275
276 NetReceive(buffer, length);
277 if (++rx_tail >= CFG_MACB_RX_RING_SIZE)
278 rx_tail = 0;
279 reclaim_rx_buffers(macb, rx_tail);
280 } else {
281 if (++rx_tail >= CFG_MACB_RX_RING_SIZE) {
282 wrapped = 1;
283 rx_tail = 0;
284 }
285 }
286 }
287
288 return 0;
289}
290
291static int macb_phy_init(struct macb_device *macb)
292{
293 struct eth_device *netdev = &macb->netdev;
294 u32 ncfgr;
295 u16 phy_id, status, adv, lpa;
296 int media, speed, duplex;
297 int i;
298
299 /* Check if the PHY is up to snuff... */
300 phy_id = macb_mdio_read(macb, MII_PHYSID1);
301 if (phy_id == 0xffff) {
302 printf("%s: No PHY present\n", netdev->name);
303 return 0;
304 }
305
306 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
307 macb_mdio_write(macb, MII_ADVERTISE, adv);
308 printf("%s: Starting autonegotiation...\n", netdev->name);
309 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
310 | BMCR_ANRESTART));
311
312#if 0
313 for (i = 0; i < 9; i++)
314 printf("mii%d: 0x%04x\n", i, macb_mdio_read(macb, i));
315#endif
316
317 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
318 status = macb_mdio_read(macb, MII_BMSR);
319 if (status & BMSR_ANEGCOMPLETE)
320 break;
321 udelay(100);
322 }
323
324 if (status & BMSR_ANEGCOMPLETE)
325 printf("%s: Autonegotiation complete\n", netdev->name);
326 else
327 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
328 netdev->name, status);
329
330 if (!(status & BMSR_LSTATUS)) {
331 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
332 udelay(100);
333 status = macb_mdio_read(macb, MII_BMSR);
334 if (status & BMSR_LSTATUS)
335 break;
336 }
337 }
338
339 if (!(status & BMSR_LSTATUS)) {
340 printf("%s: link down (status: 0x%04x)\n",
341 netdev->name, status);
342 return 0;
343 } else {
344 lpa = macb_mdio_read(macb, MII_LPA);
345 media = mii_nway_result(lpa & adv);
346 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
347 ? 1 : 0);
348 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
349 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
350 netdev->name,
351 speed ? "100" : "10",
352 duplex ? "full" : "half",
353 lpa);
354
355 ncfgr = macb_readl(macb, NCFGR);
356 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
357 if (speed)
358 ncfgr |= MACB_BIT(SPD);
359 if (duplex)
360 ncfgr |= MACB_BIT(FD);
361 macb_writel(macb, NCFGR, ncfgr);
362 return 1;
363 }
364}
365
366static int macb_init(struct eth_device *netdev, bd_t *bd)
367{
368 struct macb_device *macb = to_macb(netdev);
369 unsigned long paddr;
370 u32 hwaddr_bottom;
371 u16 hwaddr_top;
372 int i;
373
374 /*
375 * macb_halt should have been called at some point before now,
376 * so we'll assume the controller is idle.
377 */
378
379 /* initialize DMA descriptors */
380 paddr = macb->rx_buffer_dma;
381 for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) {
382 if (i == (CFG_MACB_RX_RING_SIZE - 1))
383 paddr |= RXADDR_WRAP;
384 macb->rx_ring[i].addr = paddr;
385 macb->rx_ring[i].ctrl = 0;
386 paddr += 128;
387 }
388 for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) {
389 macb->tx_ring[i].addr = 0;
390 if (i == (CFG_MACB_TX_RING_SIZE - 1))
391 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
392 else
393 macb->tx_ring[i].ctrl = TXBUF_USED;
394 }
395 macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
396
397 macb_writel(macb, RBQP, macb->rx_ring_dma);
398 macb_writel(macb, TBQP, macb->tx_ring_dma);
399
400 /* set hardware address */
401 hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
402 macb_writel(macb, SA1B, hwaddr_bottom);
403 hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
404 macb_writel(macb, SA1T, hwaddr_top);
405
406 /* choose RMII or MII mode. This depends on the board */
407#ifdef CONFIG_RMII
408 macb_writel(macb, USRIO, 0);
409#else
410 macb_writel(macb, USRIO, MACB_BIT(MII));
411#endif
412
413 if (!macb_phy_init(macb))
414 return 0;
415
416 /* Enable TX and RX */
417 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
418
419 return 1;
420}
421
422static void macb_halt(struct eth_device *netdev)
423{
424 struct macb_device *macb = to_macb(netdev);
425 u32 ncr, tsr;
426
427 /* Halt the controller and wait for any ongoing transmission to end. */
428 ncr = macb_readl(macb, NCR);
429 ncr |= MACB_BIT(THALT);
430 macb_writel(macb, NCR, ncr);
431
432 do {
433 tsr = macb_readl(macb, TSR);
434 } while (tsr & MACB_BIT(TGO));
435
436 /* Disable TX and RX, and clear statistics */
437 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
438}
439
440int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
441{
442 struct macb_device *macb;
443 struct eth_device *netdev;
444 unsigned long macb_hz;
445 u32 ncfgr;
446
447 macb = malloc(sizeof(struct macb_device));
448 if (!macb) {
449 printf("Error: Failed to allocate memory for MACB%d\n", id);
450 return -1;
451 }
452 memset(macb, 0, sizeof(struct macb_device));
453
454 netdev = &macb->netdev;
455
456 macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE,
457 &macb->rx_buffer_dma);
458 macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE
459 * sizeof(struct macb_dma_desc),
460 &macb->rx_ring_dma);
461 macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE
462 * sizeof(struct macb_dma_desc),
463 &macb->tx_ring_dma);
464
465 macb->regs = regs;
466 macb->phy_addr = phy_addr;
467
468 sprintf(netdev->name, "macb%d", id);
469 netdev->init = macb_init;
470 netdev->halt = macb_halt;
471 netdev->send = macb_send;
472 netdev->recv = macb_recv;
473
474 /*
475 * Do some basic initialization so that we at least can talk
476 * to the PHY
477 */
478 macb_hz = get_macb_pclk_rate(id);
479 if (macb_hz < 20000000)
480 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
481 else if (macb_hz < 40000000)
482 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
483 else if (macb_hz < 80000000)
484 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
485 else
486 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
487
488 macb_writel(macb, NCFGR, ncfgr);
489
490 eth_register(netdev);
491
492 return 0;
493}
494
495#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */
496
497#if (CONFIG_COMMANDS & CFG_CMD_MII)
498
499int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
500{
501 unsigned long netctl;
502 unsigned long netstat;
503 unsigned long frame;
504 int iflag;
505
506 iflag = disable_interrupts();
507 netctl = macb_readl(&macb, EMACB_NCR);
508 netctl |= MACB_BIT(MPE);
509 macb_writel(&macb, EMACB_NCR, netctl);
510 if (iflag)
511 enable_interrupts();
512
513 frame = (MACB_BF(SOF, 1)
514 | MACB_BF(RW, 2)
515 | MACB_BF(PHYA, addr)
516 | MACB_BF(REGA, reg)
517 | MACB_BF(CODE, 2));
518 macb_writel(&macb, EMACB_MAN, frame);
519
520 do {
521 netstat = macb_readl(&macb, EMACB_NSR);
522 } while (!(netstat & MACB_BIT(IDLE)));
523
524 frame = macb_readl(&macb, EMACB_MAN);
525 *value = MACB_BFEXT(DATA, frame);
526
527 iflag = disable_interrupts();
528 netctl = macb_readl(&macb, EMACB_NCR);
529 netctl &= ~MACB_BIT(MPE);
530 macb_writel(&macb, EMACB_NCR, netctl);
531 if (iflag)
532 enable_interrupts();
533
534 return 0;
535}
536
537int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
538{
539 unsigned long netctl;
540 unsigned long netstat;
541 unsigned long frame;
542 int iflag;
543
544 iflag = disable_interrupts();
545 netctl = macb_readl(&macb, EMACB_NCR);
546 netctl |= MACB_BIT(MPE);
547 macb_writel(&macb, EMACB_NCR, netctl);
548 if (iflag)
549 enable_interrupts();
550
551 frame = (MACB_BF(SOF, 1)
552 | MACB_BF(RW, 1)
553 | MACB_BF(PHYA, addr)
554 | MACB_BF(REGA, reg)
555 | MACB_BF(CODE, 2)
556 | MACB_BF(DATA, value));
557 macb_writel(&macb, EMACB_MAN, frame);
558
559 do {
560 netstat = macb_readl(&macb, EMACB_NSR);
561 } while (!(netstat & MACB_BIT(IDLE)));
562
563 iflag = disable_interrupts();
564 netctl = macb_readl(&macb, EMACB_NCR);
565 netctl &= ~MACB_BIT(MPE);
566 macb_writel(&macb, EMACB_NCR, netctl);
567 if (iflag)
568 enable_interrupts();
569
570 return 0;
571}
572
573#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
574
575#endif /* CONFIG_MACB */