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wdenkc6097192002-11-03 00:24:07 +00001/*
stroese2a9e02e2003-02-18 11:30:24 +00002 * (C) Copyright 2001-2003
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
39
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000043
44#define CONFIG_BAUDRATE 9600
45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
46
47#undef CONFIG_BOOTARGS
48#define CONFIG_BOOTCOMMAND "bootm fff00000"
49
50#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
51#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
52
53#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000054#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000055#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
wdenkc6097192002-11-03 00:24:07 +000056
57#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
58 CFG_CMD_PCI | \
59 CFG_CMD_IRQ | \
stroese2a9e02e2003-02-18 11:30:24 +000060 CFG_CMD_MII | \
wdenkc6097192002-11-03 00:24:07 +000061 CFG_CMD_ELF | \
wdenkc837dcb2004-01-20 23:12:12 +000062 CFG_CMD_EEPROM )
wdenkc6097192002-11-03 00:24:07 +000063
64/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
65#include <cmd_confdefs.h>
66
67#undef CONFIG_WATCHDOG /* watchdog disabled */
68
wdenkc837dcb2004-01-20 23:12:12 +000069#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000070
71/*
72 * Miscellaneous configurable options
73 */
74#define CFG_LONGHELP /* undef to save memory */
75#define CFG_PROMPT "=> " /* Monitor Command Prompt */
76#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +000077#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000078#else
wdenkc837dcb2004-01-20 23:12:12 +000079#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000080#endif
81#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
82#define CFG_MAXARGS 16 /* max number of command args */
83#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
84
wdenkc837dcb2004-01-20 23:12:12 +000085#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +000086
87#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
88#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
89
wdenkc837dcb2004-01-20 23:12:12 +000090#define CFG_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
wdenkc6097192002-11-03 00:24:07 +000091
92/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +000093#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +000094 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
95 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +000096
97#define CFG_LOAD_ADDR 0x100000 /* default load address */
98#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
99
wdenkc837dcb2004-01-20 23:12:12 +0000100#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000101
102#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
103
104/*-----------------------------------------------------------------------
105 * PCI stuff
106 *-----------------------------------------------------------------------
107 */
wdenkc837dcb2004-01-20 23:12:12 +0000108#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
109#define PCI_HOST_FORCE 1 /* configure as pci host */
110#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CONFIG_PCI /* include pci support */
113#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
114#define CONFIG_PCI_PNP /* do pci plug-and-play */
115 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000116
wdenkc837dcb2004-01-20 23:12:12 +0000117#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
118#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
119#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
120#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
121#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
122#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */
123#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
124#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000125
126/*-----------------------------------------------------------------------
127 * Start addresses for the final memory configuration
128 * (Set up by the startup code)
129 * Please note that CFG_SDRAM_BASE _must_ start at 0
130 */
131#define CFG_SDRAM_BASE 0x00000000
132#define CFG_FLASH_BASE 0xFFFC0000
133#define CFG_MONITOR_BASE CFG_FLASH_BASE
134#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
135#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
136
137/*
138 * For booting Linux, the board info and command line data
139 * have to be in the first 8 MB of memory, since this is
140 * the maximum mapped by the Linux kernel during initialization.
141 */
142#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
143/*-----------------------------------------------------------------------
144 * FLASH organization
145 */
146#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
147#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
148
149#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
150#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
151
wdenkc837dcb2004-01-20 23:12:12 +0000152#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
153#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
154#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000155/*
156 * The following defines are added for buggy IOP480 byte interface.
157 * All other boards should use the standard values (CPCI405 etc.)
158 */
wdenkc837dcb2004-01-20 23:12:12 +0000159#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
160#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
161#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000162
wdenkc837dcb2004-01-20 23:12:12 +0000163#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000164
165/*-----------------------------------------------------------------------
166 * I2C EEPROM (CAT24WC08) for environment
167 */
168#define CONFIG_HARD_I2C /* I2C with hardware support */
169#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
170#define CFG_I2C_SLAVE 0x7F
171
172#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000173#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
174/* mask of address bits that overflow into the "EEPROM chip address" */
wdenkc6097192002-11-03 00:24:07 +0000175#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
176#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
177 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000178 /* last 4 bits of the address */
wdenkc6097192002-11-03 00:24:07 +0000179#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
180#define CFG_EEPROM_PAGE_WRITE_ENABLE
181
wdenkc837dcb2004-01-20 23:12:12 +0000182#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
183#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
184#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000185 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000186
187/*-----------------------------------------------------------------------
188 * Cache Configuration
189 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200190#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
wdenkc6097192002-11-03 00:24:07 +0000191#define CFG_CACHELINE_SIZE 32 /* ... */
192#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
193#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
194#endif
195
196/*
197 * Init Memory Controller:
198 *
199 * BR0/1 and OR0/1 (FLASH)
200 */
201
202#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
203#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
204
205/*-----------------------------------------------------------------------
206 * External Bus Controller (EBC) Setup
207 */
208
wdenkc837dcb2004-01-20 23:12:12 +0000209/* Memory Bank 0 (Flash Bank 0) initialization */
210#define CFG_EBC_PB0AP 0x92015480
211#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000212
wdenkc837dcb2004-01-20 23:12:12 +0000213/* Memory Bank 1 (Uart 8bit) initialization */
214#define CFG_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
215#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000216
wdenkc837dcb2004-01-20 23:12:12 +0000217/* Memory Bank 2 (Uart 32bit) initialization */
218#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
219#define CFG_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
wdenkc6097192002-11-03 00:24:07 +0000220
wdenkc837dcb2004-01-20 23:12:12 +0000221/* Memory Bank 3 (FPGA Reset) initialization */
222#define CFG_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
223#define CFG_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000224
225/*-----------------------------------------------------------------------
226 * Definitions for initial stack pointer and data area (in DPRAM)
227 */
wdenkc837dcb2004-01-20 23:12:12 +0000228#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
229#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
230#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
stroese2a9e02e2003-02-18 11:30:24 +0000231#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
232#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000233#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000234
235/*
236 * Internal Definitions
237 *
238 * Boot Flags
239 */
240#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
241#define BOOTFLAG_WARM 0x02 /* Software reboot */
242
243#endif /* __CONFIG_H */