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wdenk0f8c9762002-08-19 11:57:05 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
18 */
19
20/* ------------------------------------------------------------------------- */
21
22/*
23 * board/config.h - configuration options, board specific
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
wdenk0f8c9762002-08-19 11:57:05 +000033#define CONFIG_MPC850 1
34#define CONFIG_MPC850SAR 1
35#define CONFIG_FADS 1
36
37#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
38#undef CONFIG_8xx_CONS_SMC2
39#undef CONFIG_8xx_CONS_NONE
40#define CONFIG_BAUDRATE 9600
41
42#if 0
43#define MPC8XX_FACT 10 /* Multiply by 10 */
44#define MPC8XX_XIN 50000000 /* 50 MHz in */
45#else
46#define MPC8XX_FACT 12 /* Multiply by 12 */
47#define MPC8XX_XIN 4000000 /* 4 MHz in */
48#endif
49#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#if 1
54#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55#else
56#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57#endif
58
59#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */
60#define CONFIG_BOOTARGS " "
61
62#undef CONFIG_WATCHDOG /* watchdog disabled */
63
64/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
65#include <cmd_confdefs.h>
66
67/*
68 * Miscellaneous configurable options
69 */
70#undef CFG_LONGHELP /* undef to save memory */
71#define CFG_PROMPT ":>" /* Monitor Command Prompt */
72#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
73#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
74#else
75#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
76#endif
77#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
78#define CFG_MAXARGS 16 /* max number of command args */
79#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
80
81#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
82#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
83
84#define CFG_LOAD_ADDR 0x00100000 /* default load address */
85
86#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
87
88#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
89
90/*
91 * Low Level Configuration Settings
92 * (address mappings, register initial values, etc.)
93 * You should know what you are doing if you make changes here.
94 */
95/*-----------------------------------------------------------------------
96 * Internal Memory Mapped Register
97 */
98#define CFG_IMMR 0xFF000000
99#define CFG_IMMR_SIZE ((uint)(64 * 1024))
100
101/*-----------------------------------------------------------------------
102 * Definitions for initial stack pointer and data area (in DPRAM)
103 */
104#define CFG_INIT_RAM_ADDR CFG_IMMR
105#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
106#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
107#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
108#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
109
110/*-----------------------------------------------------------------------
111 * Start addresses for the final memory configuration
112 * (Set up by the startup code)
113 * Please note that CFG_SDRAM_BASE _must_ start at 0
114 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
115 */
116#define CFG_SDRAM_BASE 0x00000000
wdenk2535d602003-07-17 23:16:40 +0000117#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
wdenk0f8c9762002-08-19 11:57:05 +0000118#define CFG_FLASH_BASE 0x02800000
119#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
120#if 0
121#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
122#else
123#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
124#endif
125#define CFG_MONITOR_BASE CFG_FLASH_BASE
126#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
127
128/*
129 * For booting Linux, the board info and command line data
130 * have to be in the first 8 MB of memory, since this is
131 * the maximum mapped by the Linux kernel during initialization.
132 */
133#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
134/*-----------------------------------------------------------------------
135 * FLASH organization
136 */
137#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
138#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
139
140#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
141#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
142
143#define CFG_ENV_IS_IN_FLASH 1
144#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
145#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
146
147/*-----------------------------------------------------------------------
148 * Cache Configuration
149 */
150#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
151#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
152#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
153#endif
154
155/*-----------------------------------------------------------------------
156 * SYPCR - System Protection Control 11-9
157 * SYPCR can only be written once after reset!
158 *-----------------------------------------------------------------------
159 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
160 */
161#if defined(CONFIG_WATCHDOG)
162#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
163 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
164#else
165#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
166#endif
167
168/*-----------------------------------------------------------------------
169 * SIUMCR - SIU Module Configuration 11-6
170 *-----------------------------------------------------------------------
171 * PCMCIA config., multi-function pin tri-state
172 */
173#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
174
175/*-----------------------------------------------------------------------
176 * TBSCR - Time Base Status and Control 11-26
177 *-----------------------------------------------------------------------
178 * Clear Reference Interrupt Status, Timebase freezing enabled
179 */
180#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
181
182/*-----------------------------------------------------------------------
183 * PISCR - Periodic Interrupt Status and Control 11-31
184 *-----------------------------------------------------------------------
185 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
186 */
187#define CFG_PISCR (PISCR_PS | PISCR_PITF)
188
189/*-----------------------------------------------------------------------
190 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
191 *-----------------------------------------------------------------------
192 * Reset PLL lock status sticky bit, timer expired status bit and timer *
193 * interrupt status bit - leave PLL multiplication factor unchanged !
194 */
195#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \
196 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
197
198/*-----------------------------------------------------------------------
199 * SCCR - System Clock and reset Control Register 15-27
200 *-----------------------------------------------------------------------
201 * Set clock output, timebase and RTC source and divider,
202 * power management and some other internal clocks
203 */
204#define SCCR_MASK SCCR_EBDF11
205#define CFG_SCCR (SCCR_TBS | \
206 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
207 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
208 SCCR_DFALCD00)
209
210 /*-----------------------------------------------------------------------
211 *
212 *-----------------------------------------------------------------------
213 *
214 */
215#define CFG_DER 0
216
217/* Because of the way the 860 starts up and assigns CS0 the
218* entire address space, we have to set the memory controller
219* differently. Normally, you write the option register
220* first, and then enable the chip select by writing the
221* base register. For CS0, you must write the base register
222* first, followed by the option register.
223*/
224
225/*
226 * Init Memory Controller:
227 *
228 * BR0/1 and OR0/1 (FLASH)
229 */
230/* the other CS:s are determined by looking at parameters in BCSRx */
231
232
233#define BCSR_ADDR ((uint) 0x02100000)
234#define BCSR_SIZE ((uint)(64 * 1024))
235
236#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
237#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
238
239#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
240#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
241
242/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
243#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
244
245#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
246#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
247#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
248
249/* BCSRx - Board Control and Status Registers */
250#define CFG_OR1_REMAP CFG_OR0_REMAP
251#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
252#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
253
254
255/*
256 * Memory Periodic Timer Prescaler
257 */
258
259/* periodic timer for refresh */
260#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
261
262/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
263#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
264#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
265
266/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
267#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
268#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
269
270/*
271 * MAMR settings for SDRAM
272 */
273
274/* 8 column SDRAM */
275#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
276 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
277 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
278/* 9 column SDRAM */
279#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
280 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
281 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
282
283#define CFG_MAMR 0x13a01114
284/*
285 * Internal Definitions
286 *
287 * Boot Flags
288 */
289#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
290#define BOOTFLAG_WARM 0x02 /* Software reboot */
291
292
293/* values according to the manual */
294
295
296#define PCMCIA_MEM_ADDR ((uint)0xff020000)
297#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
298
299#define BCSR0 ((uint) (BCSR_ADDR + 00))
300#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
301#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
302#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
303#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
304
305/* FADS bitvalues by Helmut Buchsbaum
306 * see MPC8xxADS User's Manual for a proper description
307 * of the following structures
308 */
309
310#define BCSR0_ERB ((uint)0x80000000)
311#define BCSR0_IP ((uint)0x40000000)
312#define BCSR0_BDIS ((uint)0x10000000)
313#define BCSR0_BPS_MASK ((uint)0x0C000000)
314#define BCSR0_ISB_MASK ((uint)0x01800000)
315#define BCSR0_DBGC_MASK ((uint)0x00600000)
316#define BCSR0_DBPC_MASK ((uint)0x00180000)
317#define BCSR0_EBDF_MASK ((uint)0x00060000)
318
319#define BCSR1_FLASH_EN ((uint)0x80000000)
320#define BCSR1_DRAM_EN ((uint)0x40000000)
321#define BCSR1_ETHEN ((uint)0x20000000)
322#define BCSR1_IRDEN ((uint)0x10000000)
323#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
324#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
325#define BCSR1_BCSR_EN ((uint)0x02000000)
326#define BCSR1_RS232EN_1 ((uint)0x01000000)
327#define BCSR1_PCCEN ((uint)0x00800000)
328#define BCSR1_PCCVCC0 ((uint)0x00400000)
329#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
330#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
331#define BCSR1_RS232EN_2 ((uint)0x00040000)
332#define BCSR1_SDRAM_EN ((uint)0x00020000)
333#define BCSR1_PCCVCC1 ((uint)0x00010000)
334
335#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000336#define BCSR2_FLASH_PD_SHIFT 28
wdenk0f8c9762002-08-19 11:57:05 +0000337#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000338#define BCSR2_DRAM_PD_SHIFT 23
wdenk0f8c9762002-08-19 11:57:05 +0000339#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
340#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
341
342#define BCSR3_DBID_MASK ((ushort)0x3800)
343#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
344#define BCSR3_BREVNR0 ((ushort)0x0080)
345#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
346#define BCSR3_BREVN1 ((ushort)0x0008)
347#define BCSR3_BREVN2_MASK ((ushort)0x0003)
348
349#define BCSR4_ETHLOOP ((uint)0x80000000)
350#define BCSR4_TFPLDL ((uint)0x40000000)
351#define BCSR4_TPSQEL ((uint)0x20000000)
352#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
353#ifdef CONFIG_MPC823
354#define BCSR4_USB_EN ((uint)0x08000000)
355#endif /* CONFIG_MPC823 */
356#ifdef CONFIG_MPC860SAR
357#define BCSR4_UTOPIA_EN ((uint)0x08000000)
358#endif /* CONFIG_MPC860SAR */
359#ifdef CONFIG_MPC860T
360#define BCSR4_FETH_EN ((uint)0x08000000)
361#endif /* CONFIG_MPC860T */
362#ifdef CONFIG_MPC823
363#define BCSR4_USB_SPEED ((uint)0x04000000)
364#endif /* CONFIG_MPC823 */
365#ifdef CONFIG_MPC860T
366#define BCSR4_FETHCFG0 ((uint)0x04000000)
367#endif /* CONFIG_MPC860T */
368#ifdef CONFIG_MPC823
369#define BCSR4_VCCO ((uint)0x02000000)
370#endif /* CONFIG_MPC823 */
371#ifdef CONFIG_MPC860T
372#define BCSR4_FETHFDE ((uint)0x02000000)
373#endif /* CONFIG_MPC860T */
374#ifdef CONFIG_MPC823
375#define BCSR4_VIDEO_ON ((uint)0x00800000)
376#endif /* CONFIG_MPC823 */
377#ifdef CONFIG_MPC823
378#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
379#endif /* CONFIG_MPC823 */
380#ifdef CONFIG_MPC860T
381#define BCSR4_FETHCFG1 ((uint)0x00400000)
382#endif /* CONFIG_MPC860T */
383#ifdef CONFIG_MPC823
384#define BCSR4_VIDEO_RST ((uint)0x00200000)
385#endif /* CONFIG_MPC823 */
386#ifdef CONFIG_MPC860T
387#define BCSR4_FETHRST ((uint)0x00200000)
388#endif /* CONFIG_MPC860T */
389#define BCSR4_MODEM_EN ((uint)0x00100000)
390#define BCSR4_DATA_VOICE ((uint)0x00080000)
391
392#define CONFIG_DRAM_50MHZ 1
393#define CONFIG_SDRAM_50MHZ
394
wdenk0f8c9762002-08-19 11:57:05 +0000395/* We don't use the 8259.
396*/
397#define NR_8259_INTS 0
398
399/* Machine type
400*/
401#define _MACH_8xx (_MACH_fads)
402
403#define CONFIG_DISK_SPINUP_TIME 1000000
404
405
406/* PCMCIA configuration */
407
408#define PCMCIA_MAX_SLOTS 2
409
410#ifdef CONFIG_MPC860
411#define PCMCIA_SLOT_A 1
412#endif
413
wdenk180d3f72004-01-04 16:28:35 +0000414#define CFG_DAUGHTERBOARD
415
wdenk0f8c9762002-08-19 11:57:05 +0000416#endif /* __CONFIG_H */