| wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * mcf5282.h -- Definitions for Motorola Coldfire 5282 |
| 3 | * |
| 4 | * Based on mcf5282sim.h of uCLinux distribution: |
| 5 | * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | /****************************************************************************/ |
| 27 | #ifndef m5282_h |
| 28 | #define m5282_h |
| 29 | /****************************************************************************/ |
| 30 | |
| 31 | /* |
| 32 | * Size of internal RAM |
| 33 | */ |
| 34 | |
| 35 | #define INT_RAM_SIZE 65536 |
| 36 | |
| 37 | |
| 38 | /* |
| 39 | * Define the 5282 SIM register set addresses. |
| 40 | */ |
| 41 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ |
| 42 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ |
| 43 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 44 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| 45 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| 46 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| 47 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| 48 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| 49 | #define MCFINTC_IRLR 0x18 /* */ |
| 50 | #define MCFINTC_IACKL 0x19 /* */ |
| 51 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
| 52 | |
| 53 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| 54 | #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ |
| 55 | |
| 56 | #define MCF5282_GPIO_PUAPAR 0x10005C |
| 57 | |
| 58 | |
| 59 | /****************************************************************************/ |
| 60 | #endif /* m5282_h */ |