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wdenk7d393ae2002-10-25 21:08:05 +00001/*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk7d393ae2002-10-25 21:08:05 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020
21#define CONFIG_SYS_TEXT_BASE 0xFFF80000
22
wdenk7d393ae2002-10-25 21:08:05 +000023/***********************************************************
wdenkf3e0de62003-06-04 15:05:30 +000024 * Note that it may also be a MIP405T board which is a subset of the
25 * MIP405
26 ***********************************************************/
27/***********************************************************
28 * WARNING:
29 * CONFIG_BOOT_PCI is only used for first boot-up and should
30 * NOT be enabled for production bootloader
31 ***********************************************************/
wdenk8bde7f72003-06-27 21:31:46 +000032/*#define CONFIG_BOOT_PCI 1*/
wdenkf3e0de62003-06-04 15:05:30 +000033/***********************************************************
wdenk7d393ae2002-10-25 21:08:05 +000034 * Clock
35 ***********************************************************/
36#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
37
Jon Loeliger8353e132007-07-08 14:14:17 -050038/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050039 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
Jon Loeliger659e2f62007-07-10 09:10:49 -050046/*
Jon Loeliger8353e132007-07-08 14:14:17 -050047 * Command line configuration.
48 */
Jon Loeliger8353e132007-07-08 14:14:17 -050049#define CONFIG_CMD_EEPROM
Jon Loeliger8353e132007-07-08 14:14:17 -050050#define CONFIG_CMD_IDE
51#define CONFIG_CMD_IRQ
52#define CONFIG_CMD_JFFS2
Jon Loeliger8353e132007-07-08 14:14:17 -050053#define CONFIG_CMD_PCI
Jon Loeliger8353e132007-07-08 14:14:17 -050054#define CONFIG_CMD_REGINFO
55#define CONFIG_CMD_SAVES
Jon Loeliger8353e132007-07-08 14:14:17 -050056
wdenk7d393ae2002-10-25 21:08:05 +000057/**************************************************************
58 * I2C Stuff:
59 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
60 * 0x53.
61 * The Atmel EEPROM uses 16Bit addressing.
62 ***************************************************************/
63
Dirk Eibach880540d2013-04-25 02:40:01 +000064#define CONFIG_SYS_I2C
65#define CONFIG_SYS_I2C_PPC4XX
66#define CONFIG_SYS_I2C_PPC4XX_CH0
67#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
68#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenk7d393ae2002-10-25 21:08:05 +000069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
71#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenk7d393ae2002-10-25 21:08:05 +000072/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
74#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenk7d393ae2002-10-25 21:08:05 +000075 /* 64 byte page write mode using*/
76 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk7d393ae2002-10-25 21:08:05 +000078
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020079#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020080#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
81#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
wdenk7d393ae2002-10-25 21:08:05 +000082
83/***************************************************************
84 * Definitions for Serial Presence Detect EEPROM address
85 * (to get SDRAM settings)
86 ***************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +000087/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
Wolfgang Denk53677ef2008-05-20 16:00:29 +020088#define SDRAM_EEPROM_READ_ADDRESS 0xA1
wdenkf3e0de62003-06-04 15:05:30 +000089*/
wdenk7d393ae2002-10-25 21:08:05 +000090/**************************************************************
91 * Environment definitions
92 **************************************************************/
wdenk7d393ae2002-10-25 21:08:05 +000093/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +020094/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
wdenk7d393ae2002-10-25 21:08:05 +000095
wdenk3e386912003-04-05 00:53:31 +000096#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenk7d393ae2002-10-25 21:08:05 +000097#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
98
99#define CONFIG_IPADDR 10.0.0.100
100#define CONFIG_SERVERIP 10.0.0.1
101#define CONFIG_PREBOOT
102/***************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000103 * defines if an overwrite_console function exists
104 *************************************************************/
wdenk7d393ae2002-10-25 21:08:05 +0000105/***************************************************************
106 * defines if the overwrite_console should be stored in the
107 * environment
108 **************************************************************/
wdenk7d393ae2002-10-25 21:08:05 +0000109
110/**************************************************************
111 * loads config
112 *************************************************************/
113#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7d393ae2002-10-25 21:08:05 +0000115
116#define CONFIG_MISC_INIT_R
117/***********************************************************
118 * Miscellaneous configurable options
119 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger8353e132007-07-08 14:14:17 -0500121#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000123#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000125#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenk7d393ae2002-10-25 21:08:05 +0000132
Stefan Roese550650d2010-09-20 16:05:31 +0200133#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese550650d2010-09-20 16:05:31 +0200134#define CONFIG_SYS_NS16550_SERIAL
135#define CONFIG_SYS_NS16550_REG_SIZE 1
136#define CONFIG_SYS_NS16550_CLK get_serial_clock()
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
139#define CONFIG_SYS_BASE_BAUD 916667
wdenk7d393ae2002-10-25 21:08:05 +0000140
141/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7d393ae2002-10-25 21:08:05 +0000143 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
144 57600, 115200, 230400, 460800, 921600 }
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
147#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk7d393ae2002-10-25 21:08:05 +0000148
wdenk7d393ae2002-10-25 21:08:05 +0000149/*-----------------------------------------------------------------------
150 * PCI stuff
151 *-----------------------------------------------------------------------
152 */
153#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
154#define PCI_HOST_FORCE 1 /* configure as pci host */
155#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
156
Gabor Juhos842033e2013-05-30 07:06:12 +0000157#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk7d393ae2002-10-25 21:08:05 +0000158#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
wdenk7d393ae2002-10-25 21:08:05 +0000159 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
161#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
162#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
163#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
164#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
165#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
166#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
167#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenk7d393ae2002-10-25 21:08:05 +0000168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7d393ae2002-10-25 21:08:05 +0000173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE 0x00000000
175#define CONFIG_SYS_FLASH_BASE 0xFFF80000
176#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
177#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
178#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenk7d393ae2002-10-25 21:08:05 +0000179
180/*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7d393ae2002-10-25 21:08:05 +0000186/*-----------------------------------------------------------------------
187 * FLASH organization
188 */
David Müller39441b32011-12-22 13:38:21 +0100189#define CONFIG_SYS_UPDATE_FLASH_SIZE
190#define CONFIG_SYS_FLASH_PROTECTION
191#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk7d393ae2002-10-25 21:08:05 +0000192
David Müller39441b32011-12-22 13:38:21 +0100193#define CONFIG_SYS_FLASH_CFI
194#define CONFIG_FLASH_CFI_DRIVER
195
196#define CONFIG_FLASH_SHOW_PROGRESS 45
197
198#define CONFIG_SYS_MAX_FLASH_BANKS 1
199#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenk7d393ae2002-10-25 21:08:05 +0000200
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200201/*
202 * JFFS2 partitions
203 *
204 */
205/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100206#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200207#define CONFIG_JFFS2_DEV "nor0"
208#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
209#define CONFIG_JFFS2_PART_OFFSET 0x00000000
210
211/* mtdparts command line support */
212/* Note: fake mtd_id used, no linux mtd map file */
213/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100214#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200215#define MTDIDS_DEFAULT "nor0=mip405-0"
216#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
217*/
wdenk63e73c92004-02-23 22:22:28 +0000218
wdenk7d393ae2002-10-25 21:08:05 +0000219/*-----------------------------------------------------------------------
wdenk63e73c92004-02-23 22:22:28 +0000220 * Logbuffer Configuration
221 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200222#undef CONFIG_LOGBUFFER /* supported but not enabled */
wdenk63e73c92004-02-23 22:22:28 +0000223/*-----------------------------------------------------------------------
224 * Bootcountlimit Configuration
225 */
226#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
227
228/*-----------------------------------------------------------------------
229 * POST Configuration
230 */
231#if 0 /* enable this if POST is desired (is supported but not enabled) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
233 CONFIG_SYS_POST_CPU | \
234 CONFIG_SYS_POST_RTC | \
235 CONFIG_SYS_POST_I2C)
wdenk63e73c92004-02-23 22:22:28 +0000236
237#endif
wdenk7d393ae2002-10-25 21:08:05 +0000238/*
239 * Init Memory Controller:
240 */
wdenk7205e402003-09-10 22:30:53 +0000241#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
242#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
243/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
244#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenk7d393ae2002-10-25 21:08:05 +0000245
David Müller39441b32011-12-22 13:38:21 +0100246#define CONFIG_BOARD_EARLY_INIT_R
wdenk7d393ae2002-10-25 21:08:05 +0000247
248/* Peripheral Bus Mapping */
249#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
250#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
251#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
252
253#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200254#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
wdenk7d393ae2002-10-25 21:08:05 +0000255
wdenk7d393ae2002-10-25 21:08:05 +0000256/*-----------------------------------------------------------------------
257 * Definitions for initial stack pointer and data area (in On Chip SRAM)
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_TEMP_STACK_OCM 1
260#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
261#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
262#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200263#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200264#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk63e73c92004-02-23 22:22:28 +0000265/* reserve some memory for POST and BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
wdenk63e73c92004-02-23 22:22:28 +0000267
wdenk63e73c92004-02-23 22:22:28 +0000268#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
wdenk63e73c92004-02-23 22:22:28 +0000270#endif
wdenk7d393ae2002-10-25 21:08:05 +0000271
wdenk7d393ae2002-10-25 21:08:05 +0000272/***********************************************************************
273 * External peripheral base address
274 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenk7d393ae2002-10-25 21:08:05 +0000276
277/***********************************************************************
278 * Last Stage Init
279 ***********************************************************************/
280#define CONFIG_LAST_STAGE_INIT
281/************************************************************
282 * Ethernet Stuff
283 ***********************************************************/
Ben Warren96e21f82008-10-27 23:50:15 -0700284#define CONFIG_PPC4xx_EMAC
wdenk7d393ae2002-10-25 21:08:05 +0000285#define CONFIG_MII 1 /* MII PHY management */
286#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenk63e73c92004-02-23 22:22:28 +0000287#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
288#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
wdenk7d393ae2002-10-25 21:08:05 +0000289/************************************************************
290 * RTC
291 ***********************************************************/
292#define CONFIG_RTC_MC146818
293#undef CONFIG_WATCHDOG /* watchdog disabled */
294
295/************************************************************
296 * IDE/ATA stuff
297 ************************************************************/
Tom Riniadf32ad2016-09-19 21:55:34 -0400298#if defined(CONFIG_TARGET_MIP405T)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
wdenkf3e0de62003-06-04 15:05:30 +0000300#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
wdenkf3e0de62003-06-04 15:05:30 +0000302#endif
303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenk7d393ae2002-10-25 21:08:05 +0000305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
307#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
308#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
309#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
310#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
311#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenk7d393ae2002-10-25 21:08:05 +0000312
313#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
314#undef CONFIG_IDE_LED /* no led for ide supported */
315#define CONFIG_IDE_RESET /* reset for ide supported... */
316#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000317#define CONFIG_SUPPORT_VFAT
wdenk7d393ae2002-10-25 21:08:05 +0000318/************************************************************
319 * ATAPI support (experimental)
320 ************************************************************/
321#define CONFIG_ATAPI /* enable ATAPI Support */
322
323/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000324 * DISK Partition support
325 ************************************************************/
wdenk7d393ae2002-10-25 21:08:05 +0000326
327/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000328 * Video support
329 ************************************************************/
wdenk7d393ae2002-10-25 21:08:05 +0000330#define CONFIG_VIDEO_LOGO
wdenk7d393ae2002-10-25 21:08:05 +0000331#undef CONFIG_VIDEO_ONBOARD
332/************************************************************
333 * USB support EXPERIMENTAL
334 ************************************************************/
Tom Riniadf32ad2016-09-19 21:55:34 -0400335#if !defined(CONFIG_TARGET_MIP405T)
wdenk7d393ae2002-10-25 21:08:05 +0000336#define CONFIG_USB_UHCI
wdenk7d393ae2002-10-25 21:08:05 +0000337
338/* Enable needed helper functions */
wdenkf3e0de62003-06-04 15:05:30 +0000339#endif
wdenk7d393ae2002-10-25 21:08:05 +0000340/************************************************************
341 * Debug support
342 ************************************************************/
Jon Loeliger8353e132007-07-08 14:14:17 -0500343#if defined(CONFIG_CMD_KGDB)
wdenk7d393ae2002-10-25 21:08:05 +0000344#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk7d393ae2002-10-25 21:08:05 +0000345#endif
346
347/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000348 * support BZIP2 compression
349 ************************************************************/
350#define CONFIG_BZIP2 1
351
wdenk7d393ae2002-10-25 21:08:05 +0000352#endif /* __CONFIG_H */